246 lines
6.6 KiB
Text
246 lines
6.6 KiB
Text
=pod
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=head1 NAME
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OPENSSL_armcap - the Arm processor capabilities vector
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=head1 SYNOPSIS
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env OPENSSL_armcap=... <application>
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=head1 DESCRIPTION
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libcrypto supports a range of Arm instruction set extensions. These
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extensions are represented by bits in the Arm processor capabilities vector.
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When libcrypto initializes, it stores the results returned by Arm CPU
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capabilities detection logic in the Arm processor capabilities vector. The
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CPU capabilities detection methods are OS-dependent, using a combination of
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information gathered by the kernel during boot, and probe functions that attempt
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to execute instructions and trap illegal instruction signals with a signal
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handler.
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To override the set of extensions available to an application, set the
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B<OPENSSL_armcap> environment variable before starting the application. The
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environment variable is assigned a numerical value that denotes the bits in
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the Arm processor capabilities vector. The arm_arch.h header file defines
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the possible values, which are explained in detail below.
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Multiple extensions are enabled by logically OR-ing the values that represent
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the desired extensions.
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B<Notes>: Attempting to executing an instruction from an extension that the
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target CPU does not support will result in an illegal instruction exception
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(SIGILL).
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Please note that not all possible values in the Arm processor capabilities
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vector are actual processor capabilities. Some values represent OpenSSL
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performance preferences for some implementations which only make sense on
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specific CPUs.
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The following extensions are defined:
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=over 4
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=item 0x0001
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Name: B<ARMV7_NEON>
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Meaning: Indicates support for the Armv7 Neon SIMD extensions on the processor.
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Effect: Enables various Armv7 Neon SIMD implementations.
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=item 0x00002
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Name: B<ARMV7_TICK>
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Meaning: Indicates support for the Armv7 system timer on the processor.
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Effect: This is used as a seed for some random number generators.
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=item 0x00004
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Name: B<ARMV8_AES>
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Meaning: Indicates support for the Armv8.0 AES hardware-acceleration extensions
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on the processor.
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Effect: Enables various Armv8.0 AES hardware-accelerated implementations.
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=item 0x00008
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Name: B<ARMV8_SHA1>
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Meaning: Indicates support for the Armv8.0 SHA1 hardware-acceleration extensions
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on the processor.
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Effect: Enables various Armv8.0 SHA1 hardware-accelerated implementations.
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=item 0x00010
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Name: B<ARMV8_SHA256>
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Meaning: Indicates support for the Armv8.0 SHA256 hardware-acceleration
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extensions on the processor.
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Effect: Enables various Armv8.0 SHA256 hardware-accelerated implementations.
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=item 0x00020
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Name: B<ARMV8_PMULL>
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Meaning: Indicates support for the Armv8.0 polynomial multiplication
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hardware-acceleration extensions on the processor.
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Effect: Used to hardware-accelerate polynomial multiplication, for example in
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AES-GCM.
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=item 0x00040
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Name: B<ARMV8_SHA512>
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Meaning: Indicates support for the Armv8.2 SHA512 hardware-acceleration
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extensions on the processor.
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Effect: Enables Armv8.2 SHA512 hardware-accelerated implementations.
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=item 0x00080
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Name: B<ARMV8_CPUID>
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Meaning: Indicates support for the Armv8.0 hardware identification extensions on
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the processor.
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Effect: Allows implementations to change their behaviour, dependant on the
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processor platform in order to achieve better performance.
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=item 0x00100
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Name: B<ARMV8_RNG>
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Meaning: Indicates support for the Armv8.5 hardware random number generation
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extensions on the processor.
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Effect: Enables hardware random number generation on supported AArch64
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processors.
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=item 0x00200
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Name: B<ARMV8_SM3>
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Meaning: Indicates support for the Armv8.2 SM3 hardware-acceleration extensions
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on the processor.
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Effect: Enables Armv8.2 SM3 hardware-accelerated implementations.
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=item 0x00400
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Name: B<ARMV8_SM4>
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Meaning: Indicates support for the Armv8.2 SM4 hardware-acceleration extensions
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on the processor.
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Effect: Enables Armv8.2 SM4 hardware-accelerated implementations.
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=item 0x00800
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Name: B<ARMV8_SHA3>
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Meaning: Indicates support for the Armv8.2 SHA3 hardware-acceleration extensions
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on the processor.
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Effect: Enables SHA3 hardware-accelerated implementations (see also
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ARMV8_HAVE_SHA3_AND_WORTH_USING).
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=item 0x01000
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Name: B<ARMV8_UNROLL8_EOR3>
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Meaning: Indicates support for the Arm EOR3 instruction, which is a part of the
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Armv8.2 SHA3 extensions, and enables 8x Loop unrolling in the AES-CTR
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implementation.
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Effect: Enables the 8x loop unrolling utilising EOR3 implementation of AES-CTR
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on platforms that support the SHA3 extension and have enough vector bandwidth.
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=item 0x02000
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Name: B<ARMV8_SVE>
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Meaning: Indicates support for the Armv8.2 SVE hardware extension on the
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processor.
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Effect: Enables various Armv8.2 SVE implementations.
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=item 0x04000
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Name: B<ARMV9_SVE2>
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Meaning: Indicates support for the Armv9.0 SVE2 hardware extension on the
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processor.
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Effect: Enables various Armv9.0 SVE2 implementations.
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=item 0x08000
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Name: B<ARMV8_HAVE_SHA3_AND_WORTH_USING>
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Meaning: Indicates support for the Armv8.2 SHA3 hardware-acceleration extensions
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on the processor, and that the hardware bandwidth is sufficient for it to be
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worth using.
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Effect: On certain Apple platforms, although the SHA3 extension is supported, it
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is actually slower than other implementations. This flag disables the
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hardware-accelerated SHA3 implementations on these platforms.
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=item 0x10000
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Name: B<ARMV8_UNROLL12_EOR3>
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Meaning: Indicates support for the Arm EOR3 instruction, which is a part of the
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Armv8.2 SHA3 extensions, and enables 12x loop unrolling in the AES-CTR
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implementation.
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Effect: Enables the 12x loop unrolling utilising EOR3 implementation of AES-CTR
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on platforms that support the extension and have enough vector bandwidth.
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=item 0x20000
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Name: B<ARMV9_SVE2_POLY1305>
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Meaning: Indicates support for the Armv9.0 SVE2 hardware extension, and enables
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its use in the Poly1305 implementation.
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Effect: Enables the Armv9.0 SVE2 Poly1305 implementation if SVE2 is enabled, the
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vector length is greater than 128 bits, and the vector length is a power of 2.
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=back
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=head1 RETURN VALUES
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Not available.
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=head1 EXAMPLES
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Check currently detected capabilities:
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$ openssl info -cpusettings
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OPENSSL_armcap=0x987d
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The detected capabilities in the above example indicate that ARMV7_NEON,
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ARMV8_AES, ARMV8_SHA1, ARMV8_SHA256, ARMV8_PMULL, ARMV8_SHA512, ARMV8_SHA3,
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ARMV8_UNROLL8_EOR3, and ARMV8_HAVE_SHA3_AND_WORTH_USING are enabled.
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Disable all instruction set extensions:
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export OPENSSL_armcap=0x00
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=head1 COPYRIGHT
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Copyright 2026 The OpenSSL Project Authors. All Rights Reserved.
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Licensed under the Apache License 2.0 (the "License"). You may not use
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this file except in compliance with the License. You can obtain a copy
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in the file LICENSE in the source distribution or at
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L<https://www.openssl.org/source/license.html>.
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=cut
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