474 lines
20 KiB
Text
474 lines
20 KiB
Text
Programmable Sound Generator (AY-3-8912)
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FEATURES
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o Full Software Control of Sound Generation
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o Interface to Most 8-Bit and 16-Bit Microprocessors
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o Three Independently Programmed Analog Outputs
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o One 8-Bit General Purpose I/O Port
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DESCRIPTION
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The AY-3-8912 Programmable Sound Generator (PSG) is
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a LSI Circuit which can produce a wide variety of complex sounds
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under software control. The AY-3-8912 is manufactured in
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the General Instrument N-Channel Ion Implant Process. Operation
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requires a single +5V power supply, a TTL compatible clock, and a
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microprocessor controller such as the General Instrument 16-bit
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CP1610 or one of the PIC1650 series of 8-bit microcomputers.
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The PSG is easily interfaced to any bus oriented system. Its flexibility
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makes it useful in applications such as music systems, sound
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effects generation, audible alarms, tone signalling and FSK modems.
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The analog sound outputs can provide 4 bits of logarithmic
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digital to analog conversion, greatly enhancing the dynamic range of
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the sounds produced.
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In order to perform sound effects while allowing the processor to
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continue its other tasks, the PSG can continue to produce sound
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after the initial commands have been given by the control processor.
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The fact that realistic sound production often involves more than one
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effect is satisfied by the three independently controllable channels
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available in the PSG.
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All of the circuit control signals are digital in nature and intended to
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be provided directly by a microprocessor/microcomputer. This
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means that one PSG can produce the full range of required sounds
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with no change in external circuitry. Since the frequency response of
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the PSG ranges from sub-audible at its lowest frequency to post-
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audible at its highest frequency, there are a few sounds which are
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beyond reproduction with only the simplest electrical connections.
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Since most applications of a microprecessor/PSG system would also
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require interfacing between outside world and the microproces-
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sor, this facility has been designed into the PSG. The AY-3-8912 has
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one port and 28 leads.
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PIN CONFIGURATION
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28 LEAD DUAL IN LINE
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AY-3-8912
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Top View
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___________________
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ANALOG CHANNEL C -|1 28|- DA0
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TEST 1 -|2 27|- DA1
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Vcc (+5V) -|3 26|- DA2
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ANALOG CHANNEL B -|4 25|- DA3
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ANALOG CHANNEL A -|5 24|- DA4
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Vss(GND) -|6 23|- DA5
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IOA7 -|7 22|- DA6
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IOA6 -|8 21|- DA7
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IOA5 -|9 20|- BC1
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IOA4 -|10 19|- BC2
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IOA3 -|11 18|- BDIR
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IOA2 -|12 17|- A8
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IOA1 -|13 16|- RESET
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IOA0 -|14 15|- CLOCK
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|___________________|
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PIN FUNCTIONS
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DA7--DA0 (input/output/high impedance)
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Data/Address 7--0: pins 21--28
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These 8 lines comprise the 8-bit bidirectional bus used by the
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microprocessor to send both data and addresses to the PSG and to
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recieve data from the PSG. In the data mode, DA7--DA0 correspond
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to Register Array bits B7-B0. In the address mode, Da3--Da0 select
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the register number (0--17) and a DA7--DA4 in conjunction with
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address inputs A8 for high order address (chip select).
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A8 (input): pin 17
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Address 8
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These "extra" address bit is made available to enable the positioning
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of the PSG (assigning a 16 word memory space) in a total 512
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word memory area rather than a 256 word memory area as defined
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by address bits DA7--DA0 alone. If the memory size does not require
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the use of this extra address line it may be left unconnected as
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it is provided with an on-chip pull-up resistor. In "noisy" environments,
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however, it is recommended that A8 is tied to +5V, if it is not to be
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used.
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_____
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RESET (input): pin 16
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For initialization/power-on purposes, applying a logic "0" (ground)
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to the Reset pin will reset all registers to "0". The Reset pin is provided
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with an on-chip pull-up resistor.
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CLOCK (input): pin 15
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This TTL-compatible input sipplies the timing reference for the
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Tone, Noise and Envelope Generators.
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BDIR, BC2, BC1 (inputs: pins 18, 19, 20
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Bus DIRection, Bus Control 2, 1
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These bus control signals are generated directly by the CP1610
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series of microprocessors to control all external and internal bus
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operations in the PSG. When using a processor other than the
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CP1610, these signals can be provided either by comparable bus
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signals or by simulating the signals on I/O lines or the processor. The
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PSG decodes these signals as illustrated in the following:
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BDIR BC2 BC1 CP1610 PSG
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FUNCTION FUNCTION
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0 0 0 NACT INACTIVE. See 010 (IAB).
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0 0 1 ADAR LATCH ADDRESS, See 111 (INTAK).
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0 1 0 IAB INACTIVE. The PSG/CPU bus is inactive DA7--DA0
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are in high impedance state.
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0 1 1 DTS READ FROM PSG. This signal causes the contents
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of the register which is currently addressed to
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appear on the PSG/CPU bus. DA7--DA0 are in the
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output mode.
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1 0 0 BAR LATCH ADDRESS. See 111 (INTAK).
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1 0 1 DW INACTIVE. See 010 (IAB).
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1 1 0 DWS WRITE TO PSG. This signal indicates that the bus
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contains register data which should be latched into
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the currently addressed register. DA7--DA0 are in
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the input mode.
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1 1 1 INTAK LATCH ADDRESS. This signal indicates that the bus
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contains a register address which should be latched
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in the PSG. DA7--DA0 are in input mode.
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While interfacing to a processor other than the CP1610 would simply
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require simulating the above decoding, the redundancies in the PSG
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functions vs bus control signals can be used to advantage in that
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only four of the eight possible decoded bus functions are required by
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the PSG. This could simplify the programming of the bus control
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signals to the following, which would only require that the processor
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generate two bus control signals (BDIR and BC1, with BC2 tied to
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+5V).
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BDIR BC2 BC1 PSG
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FUNCTION
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0 1 0 INACTIVE.
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0 1 1 READ FROM PSG.
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1 1 0 WRITE TO PSG.
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1 1 1 LATCH ADDRESS.
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ANALOG CHANNEL A, B, C (outputs): pins 5, 4, 1
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Each of these signals is the output of its corresponding D/A
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Converter, and provides an up to 1V peak-peak signal representing
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the complex sound waveshape generated by the PSG.
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IOA7--IOA0 (input/output): pins 7--14
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Input/Output A7--A0
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This parallel input/output port provides 8 bits of
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prarllel data to/from the PSG/CPU bus from/to any external devices
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connected to the IOA pins. Each pin is provided with an on-chip
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pull-up resistor, so that when in the "input" mode, all pins will
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read normally high. Therefore, the recommended method for scanning
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external switches would be to ground the input bit.
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TEST 1: pin 2
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This pin is for General Instrument test purposes only and should
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be left open - do not use as tie-point.
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Vcc: pin 3
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Nominal +5Volt power supply to the PSG.
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Vss: pin 6
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Ground reference for the PSG.
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ARCHITECTURE
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The AY-3-8912 is a register oriented Programmable Sound
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Generator (PSG). Communication between the processor and the
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PSG is based on the concept of memory-mapped I/O. Control
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commands are issued to the PSG by writing to 16 memory-mapped regis-
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ters. Each of the 16 registers within the PSG is also readable
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so that the mircroprocessor can determine, as necessary, present
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states or stored data values.
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All functions of the PSG are controlled through the 16 registers which
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once programmed, generate and sustain the sounds, thus freeing the
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system processor for other tasks.
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REGISTER ARRAY
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The principal element of the PSG is the array of 16 read/write control
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registers. These 16 registers look to the CPU as a block of memory
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and as such occupy a 16 word block out of 512 possible addresses.
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The 9 address bits (8 bits on the common data/address bus, and 1
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separate address bit A8) are decoded as follows:
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___ ___ ___ ___ ___ ___ ___ ___ ___
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| A8|DA7|DA6|DA5|DA4|DA3|DA2|DA1|DA0|
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|___|___|___|___|___|___|___|___|___|
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| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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|___|___|___|___|___|___|___|___|___|
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THRU
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___ ___ ___ ___ ___ ___ ___ ___ ___
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| 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
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|___|___|___|___|___|___|___|___|___|
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\_________________/ \_____________/
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\/ \/
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HIGH ORDER LOW ORDER
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(Chip Select) (Register No.)
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The four low order address bits select one of the 16 registers
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(R0--R15). The 5 high order address bits function as "chip selects"
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to control the tri state bidirectional buffers (when the high order
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address bits are "incorrect", the bidirectional buffers are forced to a
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high impedance state). High order address bit A8 is fixed in the
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PSG design to recognize a 1 code; high order address bits DA7--DA4
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may be maskk-programmed to any 4-bit code by a special order
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factory mask modification. Unless otherwise specified, address bits
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DA7--DA4 are programmed to recognize only a 0000 code. A valid
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high order address latches the register address (the low order 4 bits)
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in the Register Address Latch/Decode block. A latched address will
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remain valid until the receipt of a new address, enabling multiple
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reads and writes of the same register contents without the need for
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redundant re-addressing.
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Conditioning of the Register Address Latch/Decode and Bidirectional
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Buffers to recognize the bus function required (anactive,
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latch address, write data, or read) is accomplished by the Bus Control
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Decode block.
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SOUND GENERATING BLOCKS
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The basic blocks in the PSG which produce the programmed sounds
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include:
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Tone Generator produce the basic square tone frequencies
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for each channel (A, B, C)
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Noise Generator produces a frequency modulated pseudo
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random pulse width square wave output.
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Mixers combine the outputs of the Tone Generators
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and the Noise Generator. One for each channel
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(A, B, C)
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Amplitude Control provides the D/A Converters with either a
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fixed or variable amplitude pattern. The fixed
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amplitude is under direct CPU control; the
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variable amplitude is accomplished by using
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the output of the Envelope Generator.
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Envelope Generator Produces an envelope pattern which can be
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used to amplitude modulate the output of
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each Mixer
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D/A Converters the three D/A Converters each produce up to
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a 16 level output signal as determined by the
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Amplitude Control
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I/O PORT
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One additional blcoks is shown in the PSG Block Diagramm which
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has nothing directly to do with the production of sound - this is
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an I/O Port (A). Since virtually all uses or microprocessor-based
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sound would require interfacing between the outside world and the
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processor, this facility has been included in the PSG.
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Data to/from the CPU bus may be read/written to the 8-bit I/O Port
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without affecting any other function of the PSG. The I/O
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Port is TTL-compatible and is provided with internal pull-ups on
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each pin.
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OPERATION
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Since all functions of the PSG are controlled by the processor
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via a series of regiser loads, a detailed description of the PSG
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operation can best be accomplished by relating each PSG function to
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the control of its corresponding register. The function of creating or
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programming a specific sound or sound effect logically follows the
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control sequence listed:
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Operation Registers Function
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Tone Generator Control R0--R5 Program tone peroids.
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Noise Generator Control R6 Program noise peroid.
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Mixer Control R7 Enable tone and/or noise
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on selected channels.
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Amplitude Control R8--R10 Select "fixed" or "envelope-
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variable" amplitudes.
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Envelope Generator Control R11--R13 Program envelope period
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and select envelope pattern.
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Tone Generator Control
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(Registers R0, R1, R2, R3, R4, R5)
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The frequency of each square wave generated by the three Tone
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Generators (one each for Channels A, B, and C) is obtained in the
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PSG by first counting down the input clock by 16, then by further
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counting down the result by the programmed 12-bit Tone Period
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value. Each 12-bit value is obtained in the PSG by combining the
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contents of the relative Coarse and Fine Tune registers, as illustrated
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in the following:
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Coarse Tune Registers Channel Fine Tune Register
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R1 A R0
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R3 B R2
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R5 C R4
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B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
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\_________/ | \ / /
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\/ | \ / /
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NOT USED | | ______________/ /
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/ |/ ______/
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TP11 TP10 TP9 TP8 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
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12-bit Tone Period (TP) to Tone Generator
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Noise Generator Control
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(Register R6)
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The frequency of the noise source is obtained in the PSG by first
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counting down the input clock by 16, then by further counting down
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the result by the programmed 5-bit Noise Period value. This 5-bit
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value consists of the lower 5-bits (B4-B0) of register R6, as
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illustrated in the following:
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Noise Period Register R6
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B7 B6 B5 B4 B3 B2 B1 B0
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\______/ \___________/
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\/ \/
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NOT USED 5-bit Noise Period (NP)
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to Noise Generator
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Mixer Control-I/O Enable
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(Register R7)
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______
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Register R7 is a multi functional Enable register which controls the
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three Noise/Tone Mixers and the general purpose I/O Port.
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The Mixers, as previously described, combine the noise and tone
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frequencies for each of the three channels. The determination of
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combining neither/either/both noise and tone frequencies on each
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channel is made by the state of bits B5-B0 or R7.
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The direction (input or output) of the general purpose I/O Port
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(IOA) is determined by the state of bit B6 or R7.
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These functions are illustrated in the following:
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Mixer Control-U/O Enable Register R7
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B7 B6 B5 B4 B3 B2 B1 B0
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NOT USED____/ | \______/ \______/
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| __\/ \/______
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_____________/ |___________ |__________
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Input Enable Noise Enable Tone Enable <-- Function
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I/O Port A C B A C B A <-- Channel
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Amplitude Control
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(Registers R8, R9, R10)
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The amplitudes of the signals generated by each of the three D/A
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Converters (one each for Channels A, B, and C) is determined by the
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contents of the lower 5 bits (B4--B0) of registers R8, R9, and R10 as
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illustrated in the following:
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Amplitude Control Register Channel
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R8 A
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R9 B
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R10 C
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B7 B6 B5 B4 B3 B2 B1 B0
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\______/ | \________/
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\/ | \/
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NOT USED | L3 L2 L1 L0
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| 4-bit "fixed" amplitude Level.
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amplitude "Mode"
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Envelope Generator Control
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(Registers R11, R12, R13)
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To accomplish the generation of fairly complex envelope patterns,
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two independent methods of control are provided in the PSG: first, it
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is possible to vary the frequency of the envelope using registers R11
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and R12; and second, the relative shape and cycle pattern of the
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envelope can be varied using register R13. The following paragraphs
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explain the details of the envelope control functions, describing
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first the envelope period control and then the envelope shape/cycle
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control.
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ENVELOPE PERIOD CONTROL (Registers R11, R12)
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The frequency of the envelope is obtained in the PSG by first
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counting down the input clock by 256, then by further counting down
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the result by the programmed 16-bit Envelope Peroid value. This
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16-bit value is obtained in the PSG by combining the contents of the
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Envelope Coarse and Fine Tune registers, as illustrated in the
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following:
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Envelope Envelope
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Coarse Tune Registers Fine Tune Register
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R12 R11
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__ B7 B6 B5 B4 B3 B2 B1 B0 __ B7 B6 B5 B4 B3 B2 B1 B0
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/ \ / \
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/ \ / \
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/ \ / \
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/ \ / \
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EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
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16-bit Envelope Period (EP) to Envelope Generator
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ENVELOPE SHAPE/CYCLE CONTROL (Register R13)
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The Envelope Generator further counts down the envelope frequency
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by 16, producing a 16-state per cycle envelope pattern as
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defined by its 4-bit counter output, E3, E2, E1, E0. The particular shape
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and cycle pattern of any desired envelope is accomplished by
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controlling the count pattern (count up/count down) of the 4-bit
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counter and by defining a single-cycle or repeat-cycle pattern.
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This envelope shape/cycle control is contained in the lower 4 bits
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(B3--B0) of register R13. Each of these 4 bits controls a function in
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the envelope generator, as illustrated in the following:
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Envelope Shape/Cycle Control Register (R13)
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B7 B6 B5 B4 B3 B2 B1 B0 Function
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\_________/ I I I I_____ Hold \
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\/ I I I________ Alternate I To Envelope
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NOT USED I I___________ Attack I Generator
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I______________ Continue /
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I/O Port Data Store
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(Register R14)
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Register R14 functions as intermediate data storage register
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between PSG/CPU data bus (DA0--DA7) and the I/O port (IOA7--IOA0).
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Using register 14 for the transfer of I/O data has no effect on
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sound generation.
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D/A Converter Operation
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Since the primary use of the PSG is to produce sound for the highly
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imperfect amplitude detection mechanism of the human ear, the D/A
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conversion is performed in logarithmic steps with a normalized
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voltage range of from 0 to 1 Volt. The specific amplitude control of
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each of the three D/A Converters is accomplished by the three sets of
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4-bit outputs of the Amplitude Control block, while the Mixer outputs
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provide the base signal frequency (Noise and/or Tone).
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