189 lines
10 KiB
Markdown
189 lines
10 KiB
Markdown
# NATIVE-PERF-PLAN: match hand-coded native, per port
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Directive (Scott, 2026-07-06): floor parity against the IIgs is not the
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bar anymore -- "still way too slow across the board." The new target is
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**each port within ~1.5x of what hand-coded native technique achieves on
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that hardware**, proven by cycle-math ceilings and workload benchmark
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rows, not vibes. The IIgs-floor rule remains a secondary invariant
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(never ship a 68k port slower than the 65816).
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Why the current table lies about games: UBER measures best-case single
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ops (aligned sprite x, one tile, one call). Real games pay (a) the
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alignment cliff -- only aligned-x sprite draws are compiled; other x
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falls to interpreters/per-pixel walkers 3-20x slower -- and (b) a
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measured ~35-50% per-call wrapper tax (dispatch + validation +
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dirty-mark) around cores that are already at silicon parity, and (c)
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have no batch paths, so a tilemap repaint pays that tax per tile.
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Frame-budget reality check (2026-07-06 table): at 25% CPU and 50/60 Hz,
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~3 sprites/frame on ST/Amiga/IIgs; a 40x25 tilemap repaint costs
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~0.44-0.64s on the 68k ports. Hand-coded games on these machines did
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far better. Close that gap.
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Ground rules (inherited from PERF-AUDIT-PLAN, all still binding):
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- Source toolchains/env.sh before any make; delete stale binaries after
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.s edits; Scott owns git; style rules apply.
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- Every phase is hash-gated: existing goldens stay bit-identical
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(diff-uber-hashes 45/45 x4) unless a phase EXPLICITLY adds rows, in
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which case new goldens are frozen only after 4-port cross-identity.
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- Every phase ends with a 4-port bench + PERF.md regeneration.
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- Cycle models are hypotheses; the emulator measurement decides (lesson:
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the fillCircle asm probe and the 17% ST clock bug).
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## Phase 0 -- Ceilings + honest workload rows [items 1+2 DONE 2026-07-06]
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### Item 1 RESULT -- native-technique ceilings (cycle-math, emulator-class)
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Ops/sec, hand-coded best technique per port. "Meas" = current UBER
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(2026-07-06, millis clock). Gap = ceiling / measured. Full derivations
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with instruction-level arithmetic are in the Phase-0 workflow reports
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(session scratchpad); re-derive on demand -- the arithmetic styles were
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validated where models met measurements (ST present model 53/sec vs 56
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measured; IIgs 29/sec present ceiling already in PERF.md).
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| Op (16x16 sprite, 8x8 tile) | ST ceiling | meas | Amiga ceiling | meas | IIgs ceiling | meas | DOS ceiling | meas |
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|---|---|---|---|---|---|---|---|---|
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| Sprite draw, arbitrary x | ~2,235-2,750 (pre-shifted movem RMW) | 585 aligned / far less unaligned | ~3,600-4,300 (blitter cookie-cut; CPU-compiled ~1,350) | 903 aligned only | 4,300 aligned / 2,490 odd (compiled stores) | 907 | ~11,000 | 6,094 |
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| Sprite save or restore | ~5,300 (move.l window) | 703/553 | ~6,300-7,400 (A->D blit) | 567/553 | ~2,520 (MVN) | 543/568 | ~14,500-18,000 | 8,964/5,744 |
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| Tile paste 8x8 | ~12,700-15,500 | 1,574 | ~10,700 | 2,253 | ~5,830 | 1,803 | ~57,000 | 9,454 |
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| 40-tile row repaint | 352-880 | -- | ~316 | -- | ~190 | -- | ~1,900 | -- |
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| Present (native answer) | page flip ~free + dirty bands (full copy ~53/s) | 56 | page flip ~free (8 copper pokes; full blit ~110/s) | 362* | dirty bands (full PEI 20-29/s; real HW ~14-32) | 68* | dirty bands (real ISA full blast 10-31 fps!) | 354* |
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*Present measurement artifacts found: Amiga/DOS measured presents
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EXCEED their physical full-copy ceilings because UBER's timed present
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loop never re-dirties the stage -- after the first copy it measures the
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dirty-union idle early-out, not a copy. IIgs 68 is the known SEI
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inflation. The gameFrame workload row (below) fixes this by dirtying
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every call.
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Headline: the wrapper tax is universal and dominates -- tile paste runs
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3-6x (up to ~10x ST, ~90% overhead DOS) below hand-coded ceilings on
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EVERY port with cores already at parity; IIgs C glue measured at
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~800-4,000 cycles per call (jlDrawPixel = 820 cycles for a 1-byte op).
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Sprite ceilings are 2.5-4x above current aligned numbers (ST via
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movem long-RMW + all 16 phases; Amiga via the BLITTER, which also
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frees the CPU -- its compiled-CPU path caps at ~1,350).
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### Item 2 RESULT -- alignment-cliff code truth (supersedes all memory)
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SPRITE_SHIFT_INDEX (spriteInternal.h:24-30): Amiga x&7, ST
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(x&7)?2:((x>>3)&1), chunky (IIgs/DOS) x&1. Emitters:
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| Port | DRAW compiled | SAVE/RESTORE compiled | Fallback at NOT_COMPILED |
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|---|---|---|---|
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| IIgs | shifts 0+1 = EVERY x | shifts 0+1 = every x | (n/a -- no cliff) |
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| DOS | shifts 0+1 = EVERY x | shifts 0+1 = every x | (n/a -- no cliff) |
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| ST | 0,1 only (x%8==0) | NEVER (stubs) | draw: byte-wide shifted c2p walker (hal.c:1815+); save/restore: asm byte copy when x%8==0 else per-pixel pair walker |
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| Amiga | shift 0 ONLY (x%8==0) | NEVER (stubs) | draw: shifted c2p walker (hal.c:1491); save/restore: plane-major copy when x%8==0 else pair walker |
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So the cliff is 68k-ONLY: 7/8 x positions run walkers on ST/Amiga, and
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jlSpriteSaveAndDraw's combined fast path NEVER fires on 68k (SAVE never
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compiled). IIgs/DOS need nothing in Phase 1.
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Phase-1 design constraints discovered: (a) ST's shift-2 bucket cannot
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hold compiled code -- ST needs SPRITE_SHIFT_INDEX changed to x&7 (a
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dispatcher-contract change) plus emitter support; (b) routineOffsets
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are uint16_t so one sprite's compiled bytes must stay < 64KB -- 8 DRAW
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variants of a mixed 32x32 (~8-16KB each) blow it; needs selective
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emission or offset-scheme change (16x16 sprites fit fine); (c) the
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jlSpriteRestoreUnder gate accepts only copyBytes == bytesPerRow or +1
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(spriteCompile.c:547-552) -- planar shifted saves record +4, so the
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gate must widen or 7/8 alignments stay interpreted even after emitters
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land; (d) stale doc: sprite.h:32-40 contradicts spriteInternal.h:16-23
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(fix during Phase 1); (e) uber.c:972 comment claims Amiga has 8
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variants -- aspirational, false today.
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### Item 3 -- workload rows [IN PROGRESS]
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Four rows appended AFTER the surfaceMarkDirtyRect timeOp (cumulative-
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hash safety: correctness checks clear the stage first, so the frozen 45
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stay bit-identical; Phase-7 precedent):
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- "jlSpriteDraw unaligned" -- x=71,y=120 (odd AND x%8==7: worst case on
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all four ports simultaneously).
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- "jlSpriteDraw sweep16" -- all 16 x phases (208..223) inside ONE call
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so the op is idempotent regardless of per-port iteration counts.
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- "jlTilePaste map 10x5" -- 50 pastes of two SNAPPED patterned tiles
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(tile pixels are platform-private; only snap round-trips portably).
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- "gameFrame composite" -- 256x96 repaint + 16 HUD tiles + 3 sprite
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saveAndDraw + 3 restores + present, net-idempotent per call; all
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sprite x mod-16-aligned so this row isolates wrapper tax + present
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(rows above own the alignment signal). Also fixes the present-row
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artifact (dirties every call).
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Golden contract goes 45 -> 49. Refreeze procedure: regression gate
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first (each port: exactly 45 match + 4 extra vs OLD golden), then
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cross-identity (49/49 IIgs vs each), only then freeze + regenerate
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PERF.md.
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Gate: ceilings documented (DONE above); new rows golden'd x4; existing
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45 untouched.
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## Phase 1 -- Kill the alignment cliff
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All-shift compiled sprites everywhere. ST: emit shifts covering all
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x%16 phases in spriteEmitInterleaved68k (pre-shifted plane bytes +
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masks spanning byte halves/groups; the Amiga 8-variant planar emitter
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is the proven template). IIgs/DOS: odd-x nibble-shifted DRAW variants
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(chunky). Save/restore already widen via shift where applicable --
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verify per port. Arena sizing: 8x DRAW variants (Amiga precedent:
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8-32KB arena; re-check DEFAULT_CODEGEN_BYTES per port).
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Gate: unaligned-sprite UBER rows reach ~parity with aligned rows on
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every port; goldens hold.
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## Phase 2 -- Strip the per-op tax
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Plane-pointer caching (kill per-draw jlpSurfacePlanePtr x4), flattened
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hot-op dispatch, inline dirty marks for the remaining hot ops (extend
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the 2026-07-06 surfaceMarkDirtyRows inline that bought 2-5%), remove
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redundant validation layers (core wrapper already proves s/bounds).
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Gate: small-op rows (tileFill/Paste/Copy, sprite ops, fillRect small)
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move measurably toward Phase-0 ceilings on all ports; goldens hold.
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## Phase 3 -- Batch APIs
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jlTileMapPaste (N tiles, one validation, one dirty union -- the
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jlDrawText pattern generalized) + sprite batch draw/save/restore.
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API shape needs Scott's sign-off before landing in public headers.
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Gate: tilemap workload row approaches ceiling (per-tile overhead ~0);
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goldens hold (new API rows get their own goldens).
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## Phase 4 -- Port-native heavy weapons
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Amiga: blitter cookie-cut sprite draw for larger-than-16x16 objects;
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blitter tile/tilemap paste evaluation. ST: evaluate movem-based
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row engines + restore-from-clean-buffer strategy for backgrounds.
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IIgs: PEI-slam variants for batch paths where applicable.
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Gate: per-op measurements vs ceilings; keep only what beats the
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compiled-CPU path on the emulator (fillCircle lesson: no dead asm).
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## Phase 5 -- Acceptance
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Every workload row within ~1.5x of its Phase-0 ceiling per port, or a
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documented cycle-proof that the remaining gap is structural (e.g. ST
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interleaved-planar RMW). PERF.md gets a ceilings column. Update the
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perf-directive memory with the outcome.
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## Progress tracker
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- [x] Phase 0 COMPLETE 2026-07-06. Ceilings + code-truth in this file
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(above); four workload rows landed in uber.c and golden'd: regression
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gate exactly 45 match + 4 extras on every port, cross-identity 49/49
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x4 (bonus: sweep16 validated the ST/Amiga shifted c2p walkers pixel-
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perfect at all 14 untested phases). Golden contract is now 49 lines.
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BASELINE the later phases must move (ops/sec, millis clock):
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jlSpriteDraw unaligned: ST 40 (5% of floor!) | Amiga 75 (9%) |
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IIgs 842 | DOS 5115 -- vs aligned 607/903/902/6218 = the
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15x/12x 68k cliff, Phase 1's gate.
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jlSpriteDraw sweep16 (x16 = draws/sec): ST 32 | Amiga 80 |
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IIgs 896 | DOS 5648 -- real arbitrary-x sprite rate.
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jlTilePaste map 10x5 (x50 = tiles/sec): ST 1600 | Amiga 2300 |
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IIgs 1750 | DOS 10000 -- Phase 2/3's gate (ceilings say
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10-15k on 68k, 57k DOS).
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gameFrame composite: ST 9 | Amiga 18 | IIgs 10 | DOS 18 fps --
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the bottom-line number; the program ends when this is at/near
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the port's refresh-limited ceiling or a documented structural
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bound.
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- [ ] Phase 1 (68k all-shift emitters + save/restore emitters;
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constraints (a)-(e) in the Phase-0 item-2 section above)
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- [ ] Phase 2
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- [ ] Phase 3
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- [ ] Phase 4
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- [ ] Phase 5
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