406 lines
24 KiB
Markdown
406 lines
24 KiB
Markdown
# NATIVE-PERF-PLAN: match hand-coded native, per port
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Directive (Scott, 2026-07-06): floor parity against the IIgs is not the
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bar anymore -- "still way too slow across the board." The new target is
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**each port within ~1.5x of what hand-coded native technique achieves on
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that hardware**, proven by cycle-math ceilings and workload benchmark
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rows, not vibes. The IIgs-floor rule remains a secondary invariant
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(never ship a 68k port slower than the 65816).
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Why the current table lies about games: UBER measures best-case single
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ops (aligned sprite x, one tile, one call). Real games pay (a) the
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alignment cliff -- only aligned-x sprite draws are compiled; other x
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falls to interpreters/per-pixel walkers 3-20x slower -- and (b) a
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measured ~35-50% per-call wrapper tax (dispatch + validation +
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dirty-mark) around cores that are already at silicon parity, and (c)
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have no batch paths, so a tilemap repaint pays that tax per tile.
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Frame-budget reality check (2026-07-06 table): at 25% CPU and 50/60 Hz,
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~3 sprites/frame on ST/Amiga/IIgs; a 40x25 tilemap repaint costs
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~0.44-0.64s on the 68k ports. Hand-coded games on these machines did
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far better. Close that gap.
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Ground rules (inherited from PERF-AUDIT-PLAN, all still binding):
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- Source toolchains/env.sh before any make; delete stale binaries after
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.s edits; Scott owns git; style rules apply.
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- Every phase is hash-gated: existing goldens stay bit-identical
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(diff-uber-hashes 45/45 x4) unless a phase EXPLICITLY adds rows, in
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which case new goldens are frozen only after 4-port cross-identity.
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- Every phase ends with a 4-port bench + PERF.md regeneration.
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- Cycle models are hypotheses; the emulator measurement decides (lesson:
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the fillCircle asm probe and the 17% ST clock bug).
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## Phase 0 -- Ceilings + honest workload rows [items 1+2 DONE 2026-07-06]
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### Item 1 RESULT -- native-technique ceilings (cycle-math, emulator-class)
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Ops/sec, hand-coded best technique per port. "Meas" = current UBER
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(2026-07-06, millis clock). Gap = ceiling / measured. Full derivations
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with instruction-level arithmetic are in the Phase-0 workflow reports
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(session scratchpad); re-derive on demand -- the arithmetic styles were
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validated where models met measurements (ST present model 53/sec vs 56
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measured; IIgs 29/sec present ceiling already in PERF.md).
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| Op (16x16 sprite, 8x8 tile) | ST ceiling | meas | Amiga ceiling | meas | IIgs ceiling | meas | DOS ceiling | meas |
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|---|---|---|---|---|---|---|---|---|
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| Sprite draw, arbitrary x | ~2,235-2,750 (pre-shifted movem RMW) | 585 aligned / far less unaligned | ~3,600-4,300 (blitter cookie-cut; CPU-compiled ~1,350) | 903 aligned only | 4,300 aligned / 2,490 odd (compiled stores) | 907 | ~11,000 | 6,094 |
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| Sprite save or restore | ~5,300 (move.l window) | 703/553 | ~6,300-7,400 (A->D blit) | 567/553 | ~2,520 (MVN) | 543/568 | ~14,500-18,000 | 8,964/5,744 |
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| Tile paste 8x8 | ~12,700-15,500 | 1,574 | ~10,700 | 2,253 | ~5,830 | 1,803 | ~57,000 | 9,454 |
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| 40-tile row repaint | 352-880 | -- | ~316 | -- | ~190 | -- | ~1,900 | -- |
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| Present (native answer) | page flip ~free + dirty bands (full copy ~53/s) | 56 | page flip ~free (8 copper pokes; full blit ~110/s) | 362* | dirty bands (full PEI 20-29/s; real HW ~14-32) | 68* | dirty bands (real ISA full blast 10-31 fps!) | 354* |
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*Present measurement artifacts found: Amiga/DOS measured presents
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EXCEED their physical full-copy ceilings because UBER's timed present
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loop never re-dirties the stage -- after the first copy it measures the
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dirty-union idle early-out, not a copy. IIgs 68 is the known SEI
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inflation. The gameFrame workload row (below) fixes this by dirtying
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every call.
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Headline: the wrapper tax is universal and dominates -- tile paste runs
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3-6x (up to ~10x ST, ~90% overhead DOS) below hand-coded ceilings on
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EVERY port with cores already at parity; IIgs C glue measured at
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~800-4,000 cycles per call (jlDrawPixel = 820 cycles for a 1-byte op).
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Sprite ceilings are 2.5-4x above current aligned numbers (ST via
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movem long-RMW + all 16 phases; Amiga via the BLITTER, which also
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frees the CPU -- its compiled-CPU path caps at ~1,350).
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**ERRATUM 2026-07-07: every ST "meas" number above (and every ST
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number anywhere dated before 2026-07-07) was captured with ~49.5% of
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the CPU consumed by the idle 12.3 kHz Timer-A audio ISR that
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jlpAudioInit started unconditionally (fixed in src/atarist/audio.c:
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demand-driven pump; PERF.md artifact #4). Honest ST values are ~2x the
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table above: tile paste 3,203/s (gap to ceiling 4.0-4.8x, not ~10x),
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aligned sprite draw 1,188/s (gap 1.9-2.3x), gameFrame 19 fps. The
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probe also measured the true ST layer split for tile paste: port op
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~1,094 cyc + dirty mark ~804 + wrapper/call ~590 = 2,484 cyc/call,
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within ~11% of instruction-count models (the remainder is ST 4-cycle
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bus rounding) -- the cycle-model methodology is validated. Amiga
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layer split from the same probe: full call ~3,120 cyc, port op alone
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~1,719 (chip-RAM contention), steady-state mark ~970. Amiga/DOS/IIgs
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audited for the same bug class: clean (~1.8% / ~0.5% / 0% idle).**
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### Item 2 RESULT -- alignment-cliff code truth (supersedes all memory)
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SPRITE_SHIFT_INDEX (spriteInternal.h:24-30): Amiga x&7, ST
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(x&7)?2:((x>>3)&1), chunky (IIgs/DOS) x&1. Emitters:
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| Port | DRAW compiled | SAVE/RESTORE compiled | Fallback at NOT_COMPILED |
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|---|---|---|---|
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| IIgs | shifts 0+1 = EVERY x | shifts 0+1 = every x | (n/a -- no cliff) |
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| DOS | shifts 0+1 = EVERY x | shifts 0+1 = every x | (n/a -- no cliff) |
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| ST | 0,1 only (x%8==0) | NEVER (stubs) | draw: byte-wide shifted c2p walker (hal.c:1815+); save/restore: asm byte copy when x%8==0 else per-pixel pair walker |
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| Amiga | shift 0 ONLY (x%8==0) | NEVER (stubs) | draw: shifted c2p walker (hal.c:1491); save/restore: plane-major copy when x%8==0 else pair walker |
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So the cliff is 68k-ONLY: 7/8 x positions run walkers on ST/Amiga, and
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jlSpriteSaveAndDraw's combined fast path NEVER fires on 68k (SAVE never
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compiled). IIgs/DOS need nothing in Phase 1.
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Phase-1 design constraints discovered: (a) ST's shift-2 bucket cannot
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hold compiled code -- ST needs SPRITE_SHIFT_INDEX changed to x&7 (a
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dispatcher-contract change) plus emitter support; (b) routineOffsets
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are uint16_t so one sprite's compiled bytes must stay < 64KB -- 8 DRAW
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variants of a mixed 32x32 (~8-16KB each) blow it; needs selective
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emission or offset-scheme change (16x16 sprites fit fine); (c) the
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jlSpriteRestoreUnder gate accepts only copyBytes == bytesPerRow or +1
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(spriteCompile.c:547-552) -- planar shifted saves record +4, so the
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gate must widen or 7/8 alignments stay interpreted even after emitters
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land; (d) stale doc: sprite.h:32-40 contradicts spriteInternal.h:16-23
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(fix during Phase 1); (e) uber.c:972 comment claims Amiga has 8
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variants -- aspirational, false today.
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### Item 3 -- workload rows [IN PROGRESS]
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Four rows appended AFTER the surfaceMarkDirtyRect timeOp (cumulative-
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hash safety: correctness checks clear the stage first, so the frozen 45
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stay bit-identical; Phase-7 precedent):
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- "jlSpriteDraw unaligned" -- x=71,y=120 (odd AND x%8==7: worst case on
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all four ports simultaneously).
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- "jlSpriteDraw sweep16" -- all 16 x phases (208..223) inside ONE call
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so the op is idempotent regardless of per-port iteration counts.
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- "jlTilePaste map 10x5" -- 50 pastes of two SNAPPED patterned tiles
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(tile pixels are platform-private; only snap round-trips portably).
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- "gameFrame composite" -- 256x96 repaint + 16 HUD tiles + 3 sprite
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saveAndDraw + 3 restores + present, net-idempotent per call; all
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sprite x mod-16-aligned so this row isolates wrapper tax + present
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(rows above own the alignment signal). Also fixes the present-row
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artifact (dirties every call).
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Golden contract goes 45 -> 49. Refreeze procedure: regression gate
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first (each port: exactly 45 match + 4 extra vs OLD golden), then
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cross-identity (49/49 IIgs vs each), only then freeze + regenerate
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PERF.md.
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Gate: ceilings documented (DONE above); new rows golden'd x4; existing
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45 untouched.
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## Phase 1 -- Kill the alignment cliff
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All-shift compiled sprites everywhere. ST: emit shifts covering all
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x%16 phases in spriteEmitInterleaved68k (pre-shifted plane bytes +
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masks spanning byte halves/groups; the Amiga 8-variant planar emitter
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is the proven template). IIgs/DOS: odd-x nibble-shifted DRAW variants
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(chunky). Save/restore already widen via shift where applicable --
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verify per port. Arena sizing: 8x DRAW variants (Amiga precedent:
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8-32KB arena; re-check DEFAULT_CODEGEN_BYTES per port).
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Gate: unaligned-sprite UBER rows reach ~parity with aligned rows on
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every port; goldens hold.
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## Phase 2 -- Strip the per-op tax
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Plane-pointer caching (kill per-draw jlpSurfacePlanePtr x4), flattened
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hot-op dispatch, inline dirty marks for the remaining hot ops (extend
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the 2026-07-06 surfaceMarkDirtyRows inline that bought 2-5%), remove
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redundant validation layers (core wrapper already proves s/bounds).
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Gate: small-op rows (tileFill/Paste/Copy, sprite ops, fillRect small)
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move measurably toward Phase-0 ceilings on all ports; goldens hold.
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## Phase 3 -- Batch APIs
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jlTileMapPaste (N tiles, one validation, one dirty union -- the
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jlDrawText pattern generalized) + sprite batch draw/save/restore.
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API shape needs Scott's sign-off before landing in public headers.
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Gate: tilemap workload row approaches ceiling (per-tile overhead ~0);
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goldens hold (new API rows get their own goldens).
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## Phase 4 -- Port-native heavy weapons
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Amiga: blitter cookie-cut sprite draw for larger-than-16x16 objects;
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blitter tile/tilemap paste evaluation. ST: evaluate movem-based
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row engines + restore-from-clean-buffer strategy for backgrounds.
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IIgs: PEI-slam variants for batch paths where applicable.
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Gate: per-op measurements vs ceilings; keep only what beats the
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compiled-CPU path on the emulator (fillCircle lesson: no dead asm).
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## Phase 5 -- Acceptance
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Every workload row within ~1.5x of its Phase-0 ceiling per port, or a
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documented cycle-proof that the remaining gap is structural (e.g. ST
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interleaved-planar RMW). PERF.md gets a ceilings column. Update the
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perf-directive memory with the outcome.
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## Progress tracker
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- [x] Phase 0 COMPLETE 2026-07-06. Ceilings + code-truth in this file
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(above); four workload rows landed in uber.c and golden'd: regression
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gate exactly 45 match + 4 extras on every port, cross-identity 49/49
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x4 (bonus: sweep16 validated the ST/Amiga shifted c2p walkers pixel-
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perfect at all 14 untested phases). Golden contract is now 49 lines.
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BASELINE the later phases must move (ops/sec, millis clock):
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jlSpriteDraw unaligned: ST 40 (5% of floor!) | Amiga 75 (9%) |
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IIgs 842 | DOS 5115 -- vs aligned 607/903/902/6218 = the
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15x/12x 68k cliff, Phase 1's gate.
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jlSpriteDraw sweep16 (x16 = draws/sec): ST 32 | Amiga 80 |
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IIgs 896 | DOS 5648 -- real arbitrary-x sprite rate.
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jlTilePaste map 10x5 (x50 = tiles/sec): ST 1600 | Amiga 2300 |
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IIgs 1750 | DOS 10000 -- Phase 2/3's gate (ceilings say
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10-15k on 68k, 57k DOS).
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gameFrame composite: ST 9 | Amiga 18 | IIgs 10 | DOS 18 fps --
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the bottom-line number; the program ends when this is at/near
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the port's refresh-limited ceiling or a documented structural
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bound.
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- [~] Phase 1 DRAW SIDE COMPLETE 2026-07-06 (steps 1-4 of the
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adversary-reconciled order; save/restore = step 5 still open):
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step 1 fused per-port shift ladder (ST 16/x&15, Amiga 8, chunky 2;
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IIgs cache fields #ifdef'd) -- gated 49/49 x4 bit-identical;
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step 2 plan-based jlSpriteCompile (measure-all, uint16-cap greedy,
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draws tier 1 / save+restore atomic pairs tier 2, arena-full degrade
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to SPRITE_DEGRADE_DRAW_MASK, 68k-only even-size guard); step 3 Amiga
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all-shift JIT (accumulator merge, shift-0 byte-identical, host-
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verified); step 4 ST 16-phase draw (spriteWalk.s masked-movem walker
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+ per-phase 22B thunk + 12B/group/row pre-shifted tables). GATE:
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49/49 x4; unaligned ST 40->500 (12.5x), Amiga 75->803 (10.7x);
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sweep16 ST 2->32, Amiga 5->50; unaligned now ~82-84% of aligned on
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both. BUGS FOUND BY THE GATES: even-size guard demoted odd-sized
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IIgs/DOS routines to the interpreter (fixed: 68k-only); Amiga bench
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task stack was the shell 4KB default -- the deeper compile path
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overflowed it nondeterministically (fixed: stack 32768 in
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bench-amiga.sh + emitter accumulators to file statics).
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Steps 5+6 COMPLETE 2026-07-06 -- **PHASE 1 DONE**, final gate 49/49
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x4. Step 5: group-window save/restore emitters both ports (2 width
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classes/sprite, IIgs-MVN-style; ST raw-span move.l chains, Amiga
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plane-run move.l/move.w), format-law gates (SPRITE_SAVE_CLASS /
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SPRITE_RESTORE_CLASS / SPRITE_BACKUP_PTR_OK in spriteInternal.h;
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restore derives class from RECORDED geometry, (bx&15)==0 term is
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correctness-critical), ST HAL raw-span interpreted branch (save +
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restore switched atomically incl. the 16x16 asm reroute), planar
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metadata-probe widening, JOEY_SPRITE_BACKUP_BYTES capacity macro +
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all 4 example owners migrated and 2-aligned. SaveAndDraw's combined
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path fires on 68k at every x for the first time. Step 6:
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DEFAULT_CODEGEN_BYTES 64KB Amiga/ST; doc sweep done. RESULTS
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(floor-relative): Amiga Save 276% / Restore 236% / SaveAndDraw 160%,
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ST 203% / 163% / 107%; Amiga gameFrame 18 -> 23 fps. Host-verified
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emitted streams (objdump); every intermediate gate 49/49 x4.
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- [x] INTERLUDE 2026-07-07 (pre-Phase-2, found by the Phase-2 V1
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probe): ST idle-audio ISR tax discovered and fixed -- see the
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Phase-0 ERRATUM above and PERF.md artifact #4. All four ports
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re-gated 49/49 after a power-failure clean-rebuild recovery AND
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after the audio fix (pixels untouched). The Phase-2+ gate baselines
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are now (millis clock, post-fix): jlSpriteDraw unaligned ST 992 /
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Amiga 803 / IIgs 845 / DOS 5118; sweep16 ST 64 / Amiga 50; jlTilePaste
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single ST 3203 / Amiga 2253 / IIgs 1741 / DOS 9806; map 10x5 (x50 =
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tiles/s) ST 3100 / Amiga 2300 / IIgs 1750 / DOS 10000; gameFrame
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ST 19 / Amiga 23 / IIgs 10 / DOS 18 fps. Floor parity: the ST has
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ZERO below-floor cells for the first time; remaining below-floor is
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Amiga-only (circle family + unaligned 95% / sweep16 89%) + DOS
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audioFrameTick (gates nothing).
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- [x] Phase 2 COMPLETE 2026-07-07 (final gate 49/49 x4 + iigs-verify;
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detail below). Steps D3 closed it: R6 TMASK_BYTE macro inline
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(copyMasked +9%, loop-back needed brl past 8-bit branch range) and
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R10 iigsDrawPixelMark fused plot+mark (jlDrawPixel 3,179 -> 5,576,
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+75%; batching plotters keep the unfused inner). EXIT NUMBERS:
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tilemap tiles/s ST 4,050 / Amiga 3,750 / IIgs 2,950 / DOS 12,900
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(from 1,600 / 2,300 / 1,750 / 10,000); gameFrame ST 21 / Amiga 25 /
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IIgs 10 / DOS 19; IIgs tilePaste gap-to-ceiling 2.15x. Remaining
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per-call floor = public wrapper + one JSL/call -> Phase 3's job.
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Optional non-gating leftovers: R7 saveAndDraw consolidation, R12
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IIgs C-residue reshapes. Recon: 6-agent workflow +
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merged synthesis (12 ranked items R1-R12) + calibrated-probe layer
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split (see ERRATUM above). Step A LANDED (gate 49/49 x4):
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plane-pointer inlining via new src/amiga/amigaPlanar.h +
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src/atarist/stPlanar.h internal headers (jlpSurfacePlanePtr stanza
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deleted -- its only callers were spriteCompile.c's 68k dispatchers),
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dead-validation cleanup in both 68k HALs. Amiga sprite ops +10-23%
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(SaveUnder 1503->1853), ST +3.5-5.2%; Amiga unaligned draw now ABOVE
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floor (903 vs IIgs 845). Step B LANDED (gate 49/49 x4): whole-tile
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dirty mark specialized in tile.c (band = [bx*2, bx*2+1] with
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compile-time proof, 8-row widen unrolled ~480 cyc vs 804 measured;
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IIgs keeps its asm marker). Tile rows: ST +9-15%, Amiga +13-18%,
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DOS +24-29%, map row ST 72 / Amiga 53 / DOS 258; tileSnap (no mark)
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flat everywhere = clean control. Step C LANDED (gate 49/49 x4):
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jlDrawRect raw-edge fills + ONE mark (band-interval proof in
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draw.c) -- ST +25% / Amiga +40% / DOS +22% on the drawRect row; the
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x2 widen unroll in surfaceMarkDirtyRows is PER-PORT by measurement:
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it lifted Amiga sprite rows +4-6% but cost the ST -5% in BOTH the
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pointer-walking and counted forms (gcc-mint materializes 4 live
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pointers either way; simple loop re-measured exactly at ST
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baseline; DOS flat) -- so Amiga unrolls, everyone else keeps the
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simple loop (documented at the #if in surface.c).
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Step E1 LANDED (gate 49/49 x4): R4a = ST/Amiga tile ops moved to
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always-inline per-port headers (stTile.h / amigaTile.h; jlpTile*
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macro-aliased in port.h before the dispatch tail, headers included
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at its END so the portData==NULL fallbacks see the jlpGenericTile*
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prototypes; ST_BYTES_PER_ROW/GROUP moved to stPlanar.h;
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surface68kStTileFill8x8 extern moved to stTile.h) -- ST tiles
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+9-14%, Amiga +5-11%, DOS flat (already single-layer). R9 =
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ST/Amiga/DOS presents consume gStageScbDirty/gStagePaletteDirty
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instead of memcmp'ing 512-712-byte cached mirrors (mirrors + Amiga
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memcmpLongs deleted; stageAlloc re-arms both flags for
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jlShutdown/jlInit cycles) -- gameFrame ST 19->21 / Amiga 23->25 /
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DOS 18->19 fps. Step E2 LANDED (gate 49/49 x4): R8 Amiga 8-row
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d16(An) unrolls in amigaTile.h (fill/copy/paste/snap;
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copyMasked/pasteMono stay rolled) -- tilePaste +36%, tileSnap +52%,
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tileFill +32%, tileCopy +28%, map row 56->75. SESSION NET (from
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honest post-audio-fix baselines): map row tiles/s ST 3,100->4,000 /
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Amiga 2,300->3,750 / DOS 10,000->12,900; gameFrame ST 19->21 /
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Amiga 23->25 / DOS 18->19 (and vs the pre-audio-fix world: ST
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gameFrame 9->21). PERF.md table regenerated from the E2-gate logs.
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Step D1 LANDED (IIgs gate 49/49 + make iigs-verify framebuffer
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check; other ports covered by the D1-gate C-side pass): R2 fused
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stage-tile entries iigsTileFillMark/PasteMark/CopyMark in
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joeyDraw.s (.text.iigsFusedTile -- ONE section for entries + the
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stageTileMark helper; a cross-section 16-bit jsr wild-jumped into
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$00CFxx twice before the section-atomicity rule was learned, see
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the cross-section-jsr feedback memory). One JSL now does
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derive($01:2000 + gRowOffsetLut[by*8] + bx*4) + op via long,X +
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band widen. IIgs: tileFill +64% (3,251), tilePaste +61% (2,710),
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tileCopy +38%, map row 35->59 (+69%), gameFrame 10->11 fps;
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tilePaste gap to ceiling 3.5x -> 2.15x. port.h stage-gates the
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three macros; tile.c's tileMarkDirtyFused knob keeps
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copyMasked/pasteMono on the separate marker. Step D2 LANDED (gate
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49/49 x4): R5 spriteCompiled* dispatchers moved to
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src/core/spriteDispatch.h as always-inline, consumed only by
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sprite.c (extern decls removed from spriteInternal.h; compile-time
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machinery stays in spriteCompile.c). Sprite rows: IIgs +6-13%
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(SaveAndDraw 423), ST SaveUnder +15%, Amiga +5-11%, DOS +2-16%.
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Measurement notes recorded in PERF.md: gameFrame quantizes +/-1
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fps run-to-run; DOS unaligned-draw row is bimodal (~3,800/~5,100)
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across identical binaries -- don't chase it. REMAINING: R6
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copyMasked tmaskByte de-layering (32 jsr/call = 384 cyc + BSS
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scratch, 13-20% of the op; + optional CopyMaskedMark fusion), R10
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fused drawPixel+mark asm entry (~820 -> ~300 cyc), optional R7
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|
saveAndDraw consolidation, optional R12 IIgs C-residue reshapes.
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|
- [x] Phase 3 LANDED 2026-07-07 (goldens refrozen 49 -> 50 per the
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Phase-0 procedure; final gate 50/50 x4). jlTileMapPaste in
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include/joey/tile.h + tile.c: tileset + row-major uint8_t index map,
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|
TILE_MAP_SKIP=0xFF, one validation + one dirty union (68k/DOS);
|
|
IIgs loop specialized (hoisted stage test, base + (idx<<5) tileset
|
|
indexing with a sizeof proof -- tiles[idx] cost a 32-bit multiply
|
|
per cell on the 65816 and initially made the batch SLOWER than the
|
|
loop). New golden'd row `jlTileMapPaste 10x5` (cross-identity
|
|
52B9646B x4). RESULTS tiles/s batch vs loop: ST 8,150 (+106%,
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|
gap 1.6-1.9x) / Amiga 7,650 (+104%, gap 1.40x = INSIDE the 1.5x
|
|
target) / DOS 22,500 (+74%) / IIgs 3,000 (+2%; per-tile cost is
|
|
~93% inner JSL post-Phase-2 -- whole-map asm walker is Phase 4's
|
|
lever there). SPRITE BATCHES DESCOPED: gate measures only the
|
|
tilemap row and post-R5 sprite dispatch overhead is ~3-6%; re-add
|
|
only against a measured need + Scott's API sign-off. API shape
|
|
SIGNED OFF by Scott 2026-07-07 (tileset + row-major uint8_t map,
|
|
TILE_MAP_SKIP=0xFF, caller-owned index validity) -- the public
|
|
header contract in include/joey/tile.h is final.
|
|
- [x] Phase 4 COMPLETE 2026-07-07 (all four arms resolved; ST landed
|
|
below). IIgs WHOLE-MAP WALKER LANDED
|
|
(gate 50/50 + iigs-verify): iigsTileMapPasteMark in joeyDraw.s --
|
|
one JSL walks the index map with an incrementally-advanced dst
|
|
offset (ONE gRowOffsetLut read; +4/column, +1280/tile-row), a
|
|
22-byte stacked D-frame for the register-starved inner (map ptr,
|
|
tile-src ptr, bases, counters -- X survives the 16-store body and
|
|
carries the dst offset; Y is clobbered so the map index lives in
|
|
the frame), bank-carry-safe idx<<5 tileset add, brl on all three
|
|
wrapping branches, ONE band union tail. RESULT: IIgs jlTileMapPaste
|
|
10x5 60 -> 140 maps/s = 7,000 tiles/s (+133%), ~400 cyc/tile --
|
|
BELOW the 480-cyc single-tile hand-coded ceiling (the walker
|
|
amortizes what per-tile calls still pay). Batch row across ports:
|
|
ST 8,150 / Amiga 7,650 / IIgs 7,000 / DOS 22,500 tiles/s.
|
|
AMIGA BLITTER COOKIE-CUT SPRITE: recon complete, DEFERRED with the
|
|
design recorded -- the source side is net-new (sprite data is
|
|
fast-RAM chunky + CPU immediates; a chip-RAM pre-shift subsystem
|
|
is required), the synchronous per-call WaitBlit contract forfeits
|
|
the parallelism win below ~32x32 (all current UBER sprite rows are
|
|
16x16 = at/below the crossover), and the honest experiment needs a
|
|
new >=32x32 golden'd row measured with AND without the fence. Full
|
|
register program (BLTCON0 0x0F00|shift|0xCA cookie-cut, per-plane B,
|
|
shared A mask) + risk list in the recon (session 2026-07-07).
|
|
ST ARM LANDED 2026-07-07 (4-agent recon + adversary, then C-first
|
|
per the binding feedback): the "movem row engine" hypothesis is
|
|
DEAD -- the tile dst is a byte scatter movem cannot address, and
|
|
byte-pair word fusion loses on a barrel-shifterless 68000 (lsl.w #8
|
|
= 22 cyc > the move.b it replaces). The C incremental pair walker
|
|
(stTileMapPaste, stTile.h) measured +17% (adversary predicted the
|
|
+15-23% cap: gcc already hoists the row mulu; the 632-cyc copy body
|
|
dominates) -- that measured C ceiling justified asm, and the real
|
|
weapon is MOVEP: stTileMapPasteMovep (src/atarist/tileMap.s) does
|
|
move.l (a0)+ / movep.l d0,d16(a1) = one tile row's 4 plane bytes in
|
|
36 cyc. ST batch row 163 -> 346 ops/s = 17,300 tiles/s (2.12x, 462
|
|
cyc/tile), ABOVE the Phase-0 12,700-15,500 ceiling (it assumed
|
|
byte-move bodies). C walker stays as the odd-tileset-pointer
|
|
fallback (move.l needs an even src; jlTileT is align-1). Gate: ST
|
|
50/50 (52B9646B held) + 12-case on-emulator TILETEST proof of the
|
|
head/tail/w1/h1/skip/odd-ptr paths the golden never exercises, each
|
|
with border-ring containment. RESTORE-FROM-CLEAN-BUFFER: EXPERIMENT
|
|
RUN AND PASSED 2026-07-07 (Scott approved same day; sign-off also
|
|
ratified the jlTileMapPaste shape). jlSurfaceCopyRect is PUBLIC API
|
|
(include/joey/surface.h): same-position rect copy, clip + outward
|
|
16-px group snap UNIFORM on every port (uniform snap is what keeps
|
|
cross-port hashes identical), pixels only, dirty-marked via
|
|
surfaceMarkDirtyRect; generic chunky row-memcpy engine (DOS + both
|
|
IIgs flavors -- the IIgs stage IS plain-C writable through its
|
|
bank-$01 pixels pointer, adversary-verified), ST = strided
|
|
interleaved row memcpys, Amiga = per-plane CPU row copies (blitter
|
|
modulo variant recorded as its upgrade; CopyMemQuick unusable at
|
|
16-px grain). Documented caller hazards: snapped erase can touch
|
|
content up to 15 px outside the rect and invalidates overlapping
|
|
live sprite backups -- erase-all-then-draw-all, one mechanism per
|
|
region. STRATEGY row `gameFrameClean composite` golden'd (contract
|
|
50 -> 51, cross-identity C51FE171 x4): vs gameFrame ST 48/22 =
|
|
2.18x (bar was 1.4x) / DOS 195/19 = 10.3x / IIgs 18/10 = 1.8x /
|
|
Amiga 34/25 = 1.36x (least, as the adversary predicted: blitter
|
|
fillRect meant less repaint to delete + chip-chip copy vs fast-RAM
|
|
backup restore). A library-transparent variant stays REJECTED (the
|
|
ST present source is the composited shadow, sprites corrupt it
|
|
pre-present; a clean source means a third 32KB buffer + routing
|
|
API by another name). IIGS
|
|
PEI-SLAM: evaluated and REJECTED -- models ~+28% on the map walker
|
|
but holds SEI for the whole map (~5.6 ms at 10x5; audio ISR jitter)
|
|
and the VBL-driven bench clock cannot honestly measure SEI ops
|
|
(SEI-inflation artifact); the landed walker already beats the
|
|
480-cyc per-tile ceiling. Batch row after Phase 4: DOS 22,500 / ST
|
|
17,300 / Amiga 7,650 / IIgs 7,000 tiles/s.
|
|
- [ ] Phase 5
|