144 lines
6.4 KiB
Markdown
144 lines
6.4 KiB
Markdown
# llvm816 — Current Status
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LLVM/Clang backend for the WDC 65816 (Apple IIgs), forked from
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llvm-mos as a separate `W65816` target.
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## What works
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End-to-end C-to-binary toolchain that produces 65816 machine code
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which runs correctly under MAME (apple2gs).
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**Language coverage at -O2 (no extra flags):**
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- All scalar arithmetic: i8 / i16 / i32 / i64 add, sub, mul, div, mod
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(signed and unsigned). Carry-chained multi-word ops via ADC/SBC pseudos
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+ ASLA16 / shift libcalls.
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- Comparisons and signed/unsigned widening (sext, zext, trunc) for all
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the above sizes.
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- Pointer arithmetic, array indexing, struct field access, struct
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return-by-value (up to 8 bytes — Pair, Vec4, double).
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- Bitfields, switch statements (verified up to ~12 cases + default),
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function pointers, function-pointer tables, indirect calls via
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`__jsl_indir` trampoline.
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- Recursion: factorial, Fibonacci, depth-3 binary-tree
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insert/sum/min/max, simple recursive quicksort.
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- Loops with goto / break / continue, nested loops, state machines.
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- `<stdarg.h>` varargs with int / long / unsigned long long mixed args.
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- Heap: `malloc` / `free` (libc.c first-fit allocator) — linked-list
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reverse with `cons` works.
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- Strings: hand-rolled `strlen`, `strcmp`, `strcpy`, `strchr`, atoi/itoa
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roundtrip.
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- Soft-float (single): all four ops + comparisons, MAME-verified.
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- Soft-double: add, sub, mul, div all return correct bit patterns;
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3-iter Newton sqrt converges. Long-running iterations may hit MAME's
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1-second sim-time budget (test config issue, not a compiler bug).
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- Inline assembly with `"a"`, `"x"`, `"y"` register constraints and
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arbitrary opcode bytes (used for the `pha;plb` bank-switch idiom).
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- C++ minimal: clang++ compiles a class with virtual + non-trivial
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ctor (vtable + RTTI omitted; no exceptions).
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- printf with `%d %x %s %c %p` and width/precision specifiers.
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- `setjmp` / `longjmp` from libgcc.s.
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- Static constructors via crt0's init_array walk.
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**Toolchain:**
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- `clang` / `llc` produce W65816 assembly + ELF object files.
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- `tools/link816` resolves cross-translation-unit refs, lays out
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text/rodata/bss, emits a flat binary the IIgs ROM can load.
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- `tools/omfEmit` produces OMF v2.1 single-segment files (the IIgs's
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native object format) for round-tripping with classic dev tools.
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- `runtime/build.sh` builds crt0, libc, soft-float, soft-double,
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libgcc into linkable objects.
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- `scripts/smokeTest.sh` runs ~80 end-to-end checks (scalar ops,
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control flow, calling conventions, MAME execution, regressions).
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Currently 100% pass.
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**ABI:**
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- arg0 in A; arg1 in X for i32-first-arg signatures; rest pushed RTL
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on the system stack with PHA. Caller deallocates via `tsc;clc;adc
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#N;tcs` or `PLY*N/2`.
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- Return: i8/i16 in A; i32 in A:X; i64 in A:X:Y plus DP[$F0..$F1] for
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the highest 16 bits.
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- Frame is empty-descending (S points to next-free); offsets account
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for the +1 skew vs LLVM's full-descending model.
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## In flight (build-system level)
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- **DWARF sidecar emission in link816** (#51): The link should produce
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a separate sidecar file with line-number / variable-location info
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that an IDE or post-mortem dumper can consume. Skeleton not yet
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written; deferred until other correctness work is done.
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## Known issues / workarounds
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- **Greedy register allocator mis-orders spills** in two patterns
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(#69, #70):
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1. Functions where both `$a` and `$x` are live-in (i64-first-arg
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with a stack-output pointer, e.g. `udivmod(i64, i64, ptr)`).
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The TAX bridging `$x` to A clobbers `$a`'s value before the
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second STA can save it.
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2. Iterative quicksort with `if/else` recursion choice: complex
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live-ranges across two `swap()` calls produce wrong arg values.
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Both reproduce only at `-O1`/`-O2` with greedy. Workaround:
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`-mllvm -regalloc=fast` for the affected translation unit.
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`softDouble.c` already requires this flag for `__muldf3` (build.sh
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applies it automatically).
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Real fix is a pre-RA pass that pre-spills critical pointer
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arguments to memory, or a targeted fix in greedy's spill-ordering
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heuristic. Material work; deferred.
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- **(d,s),y / (sr,s),y addressing wraps the bank** when Y is
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negative as 16-bit unsigned. Worked around by `W65816NegYIndY`
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rewriting the affected ops to `TAX ; LDA/STA $0000,X`. Stays
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correct for negative offsets like `arr[i-1]`.
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- **(d,s),y for stack-local pointer dereferences uses DBR**, so
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user code that switches DBR (e.g. `pha;plb` to bank 2 to reach
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IIgs hardware) must not call into a function that takes the
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address of one of its locals — the callee's `*p = v` will write
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to the wrong bank. Documented; no compiler-side mitigation
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beyond the existing DPF0 fake-physreg routing for the i64-return
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high half.
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## What's still needed for a "ship-ready" toolchain
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- **Greedy regalloc spill-ordering fix** — see above. Removes the
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need for the per-file `-regalloc=fast` workaround on
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`softDouble.c` and unblocks pattern-rich code that currently
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must be compiled at `-O0` for correctness.
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- **Round-to-nearest-even in `__divdf3`** — currently
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truncate-toward-zero, which differs from gcc by ±1 ULP in
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several test cases. Acceptable today (Newton iterations still
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converge); revisit when an exact-match test suite lands.
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- **DWARF sidecar** (#51) for source-level debugging.
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- **More of the C standard library**: `<math.h>` transcendental
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functions (sin, cos, exp, log, pow), `<string.h>` beyond what's
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hand-coded, `<stdio.h>` file I/O (`fopen`, `fread`, `fwrite`,
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`fseek`).
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- **C++ runtime support**: vtable layout for multiple inheritance,
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RTTI, exceptions (or a documented `-fno-exceptions` requirement).
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- **REP/SEP scheduling pass** (design doc §3.3): the current
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prologue picks one M-mode for the whole function based on
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whether any 8-bit accumulator value is used. A per-region
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scheduler would reduce the SEP/REP wrap overhead on i8 stores.
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- **Toolbox / IIgs system call bindings**: header files declaring
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the Apple IIgs system calls (`SystemTask`, `WaitMouseUp`,
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`DrawString`, …) with the right inline-asm dispatch glue.
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- **Real-world program coverage**: the smoke tests are
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microbenchmarks. A few known-good Apple IIgs C programs (e.g.
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a textfile pager, a small game) compiled and run end-to-end
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would catch issues no synthetic test currently exercises.
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- **Cycle-time / size benchmarks vs Calypsi 5.16**: design doc §1
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says the goal is to "match or exceed" Calypsi. We have neither
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baseline numbers nor a comparison harness yet.
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