197 lines
6 KiB
C
197 lines
6 KiB
C
/* SPDX-License-Identifier: Apache-2.0 OR MIT */
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/*
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* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
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*/
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#ifndef VDPP3_REG_H
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#define VDPP3_REG_H
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#include "vdpp2_reg.h"
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#define VDPP3_REG_OFF_DMSR (0x0080)
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#define VDPP3_REG_OFF_DCI_HIST (0x00E0)
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#define VDPP3_REG_OFF_ES (0x0100)
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#define VDPP3_REG_OFF_PYRAMID (0x0190)
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#define VDPP3_REG_OFF_BBD (0x01B0)
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#define VDPP3_REG_OFF_SHARP (0x0200)
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#define VDPP3_REG_OFF_ZME (0x2800)
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/* zme: 0x2800 - 0x2844 */
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typedef struct vdpp3_zme_reg {
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struct {
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RK_U32 bypass_en : 1;
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RK_U32 align_en : 1;
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RK_U32 reserved_1 : 2;
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RK_U32 format_in : 4;
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RK_U32 format_out : 4;
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RK_U32 reserved_2 : 19;
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RK_U32 auto_gating_en : 1;
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} reg0; /* 0x0800 */
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/* reg1 0x0804 - reg2 0x080C */
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RK_U32 reg1_3[3];
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struct {
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RK_U32 yrgb_xsd_en : 1;
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RK_U32 yrgb_xsu_en : 1;
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RK_U32 yrgb_scl_mode : 2;
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RK_U32 yrgb_ysd_en : 1;
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RK_U32 yrgb_ysu_en : 1;
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RK_U32 yrgb_yscl_mode : 2;
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RK_U32 yrgb_dering_en : 1;
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RK_U32 yrgb_gt_en : 1;
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RK_U32 yrgb_gt_mode : 2;
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RK_U32 reserved_1 : 4;
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RK_U32 yrgb_xsd_bypass : 1;
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RK_U32 yrgb_ys_bypass : 1;
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RK_U32 yrgb_xsu_bypass : 1;
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RK_U32 reserved_2 : 1;
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RK_U32 yrgb_xscl_coe_sel : 4;
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RK_U32 yrgb_yscl_coe_sel : 4;
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RK_U32 reserved_3 : 4;
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} reg4; /* 0x0810 */
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/* reg5 0x0814 - reg6 x0818 */
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RK_U32 reg5_6[2];
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struct {
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RK_U32 yrgb_dering_sen0 : 5;
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RK_U32 reserved_1 : 3;
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RK_U32 yrgb_dering_sen1 : 5;
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RK_U32 reserved_2 : 3;
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RK_U32 yrgb_dering_alpha: 5;
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RK_U32 reserved_3 : 3;
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RK_U32 yrgb_dering_delta: 5;
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RK_U32 reserved_4 : 3;
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} reg7; /* 0x081C */
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struct {
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RK_U32 yrgb_xscl_factor : 16;
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RK_U32 yrgb_xscl_offset : 16;
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} reg8; /* 0x0820 */
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struct {
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RK_U32 yrgb_yscl_factor : 16;
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RK_U32 yrgb_yscl_offset : 16;
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} reg9; /* 0x0824 */
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/* reg10 0x0828 - reg11 0x082C */
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RK_U32 reg10_11[2]; /* 0x0828 */
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struct {
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RK_U32 cbcr_xsd_en : 1;
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RK_U32 cbcr_xsu_en : 1;
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RK_U32 cbcr_xscl_mode : 2;
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RK_U32 cbcr_ysd_en : 1;
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RK_U32 cbcr_ysu_en : 1;
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RK_U32 cbcr_yscl_mode : 2;
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RK_U32 cbcr_dering_en : 1;
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RK_U32 cbcr_gt_en : 1;
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RK_U32 cbcr_gt_mode : 2;
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RK_U32 reserved_1 : 4;
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RK_U32 cbcr_xsd_bypass : 1;
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RK_U32 cbcr_ys_bypass : 1;
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RK_U32 cbcr_xsu_bypass : 1;
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RK_U32 reserved_2 : 1;
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RK_U32 cbcr_xscl_coe_sel: 4;
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RK_U32 cbcr_yscl_coe_sel: 4;
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RK_U32 reserved_3 : 4;
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} reg12; /* 0x0830 */
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/* reg13 0x0834 - reg14 0x0838 */
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RK_U32 reg13_14[2];
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struct {
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RK_U32 cbcr_dering_sen0 : 5;
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RK_U32 reserved_1 : 3;
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RK_U32 cbcr_dering_sen1 : 5;
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RK_U32 reserved_2 : 3;
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RK_U32 cbcr_dering_alpha: 5;
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RK_U32 reserved_3 : 3;
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RK_U32 cbcr_dering_delta: 5;
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RK_U32 reserved_4 : 3;
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} reg15; /* 0x083C */
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struct {
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RK_U32 cbcr_xscl_factor : 16;
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RK_U32 cbcr_xscl_offset : 16;
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} reg16; /* 0x0840 */
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struct {
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RK_U32 cbcr_yscl_factor : 16;
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RK_U32 cbcr_yscl_offset : 16;
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} reg17; /* 0x0844 */
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} RegZme3;
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/* pyramid: 0x1190 - 0x11A8 */
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typedef struct vdpp3_pyr_reg {
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struct {
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RK_U32 sw_pyramid_en : 1;
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RK_U32 reserved : 31;
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} reg0; // 0x0190
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struct {
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RK_U32 sw_pyramid_layer1_dst_addr : 32;
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} reg1; // 0x0194
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struct {
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RK_U32 sw_pyramid_layer1_dst_vir_wid : 16;
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RK_U32 reserved : 16;
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} reg2; // 0x0198
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struct {
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RK_U32 sw_pyramid_layer2_dst_addr : 32;
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} reg3; // 0x019C
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struct {
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RK_U32 sw_pyramid_layer2_dst_vir_wid : 16;
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RK_U32 reserved : 16;
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} reg4; // 0x01A0
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struct {
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RK_U32 sw_pyramid_layer3_dst_addr : 32;
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} reg5; // 0x01A4
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struct {
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RK_U32 sw_pyramid_layer3_dst_vir_wid : 16;
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RK_U32 reserved : 16;
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} reg6; // 0x01A8
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} RegPyr;
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/* bbd: 0x11B0 - 0x11B8 */
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typedef struct vdpp3_bbd_reg {
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struct {
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RK_U32 sw_det_en : 1;
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RK_U32 reserved1 : 3;
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RK_U32 sw_det_blcklmt : 8;
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RK_U32 reserved2 : 20;
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} reg0; // 0x01B0
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struct {
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RK_U32 blckbar_size_top : 12;
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RK_U32 reserved1 : 4;
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RK_U32 blckbar_size_bottom : 12;
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RK_U32 reserved2 : 4;
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} reg1; // 0x01B4
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struct {
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RK_U32 blckbar_size_left : 12;
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RK_U32 reserved1 : 4;
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RK_U32 blckbar_size_right : 12;
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RK_U32 reserved2 : 4;
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} reg2; // 0x01B8
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} RegBbd;
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typedef struct vdpp3_reg {
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RegCom2 common; /* offset: 0x1000, end: 0x106C, size: 112 */
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RegDmsr dmsr; /* offset: 0x1080, end: 0x10D0, size: 84 */
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RegHist hist; /* offset: 0x10E0, end: 0x10F0, size: 20 */
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RegEs es; /* offset: 0x1100, end: 0x117C, size: 128 */
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RegShp sharp; /* offset: 0x1200, end: 0x14a8, size: 684 */
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RegPyr pyr; /* offset: 0x0190, end: 0x11A8, size: 28 */
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RegBbd bbd; /* offset: 0x01B0, end: 0x11B8, size: 12 */
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RegZme3 zme; /* offset: 0x2000, end: 0x2844, size: 1160(valid)/2120(total) */
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} Vdpp3Regs;
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#endif /* VDPP3_REG_H */
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