155 lines
4.6 KiB
Text
Vendored
155 lines
4.6 KiB
Text
Vendored
=pod
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=head1 NAME
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OPENSSL_ppccap - the PowerPC processor capabilities vector
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=head1 SYNOPSIS
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env OPENSSL_ppccap=... <application>
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=head1 DESCRIPTION
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libcrypto supports PowerPC instruction set extensions. These extensions are
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represented by bits in the PowerPC capabilities vector. When libcrypto
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initializes, it stores the results returned by PowerPC CPU capabilities detection
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logic in the PowerPC capabilities vector. The CPU capabilities detection methods
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are OS-dependent and use a combination of information gathered by the kernel
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during boot and probe functions that attempt to execute instructions and trap
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illegal instruction signals with a signal handler.
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To override the set of extensions available to an application, you can set the
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B<OPENSSL_ppccap> environment variable before you start the application. The
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environment variable is assigned a numerical value that denotes the bits in
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the PowerPC capabilities vector. The ppc_arch.h header file states that, "Flags'
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usage can appear ambiguous, because they are set rather to reflect OpenSSL
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performance preferences than actual processor capabilities."
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Multiple extensions are enabled by logically OR-ing the values that represent the
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desired extensions.
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B<Notes>: Enabling an extension on a CPU that does not support the extension
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will result in a SIGILL crash. On AIX, all vector instructions can be disabled
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with the schedo -ro allow_vmx=0 command. DO NOT USE THIS COMMAND to disable
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vector instructions in the OS when it is running on a CPU level that supports the
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instructions without also disabling them in libcrpto via the OPENSSL_ppccap
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environment variable or the application will crash with a SIGILL.
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Currently, the following extensions are defined:
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=over 4
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=item 0x01
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Name: B<PPC_FPU64>
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This flag is obsolete.
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=item 0x02
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Name: B<PPC_ALTIVEC>
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Meaning: Use AltiVec (aka VMX) instructions. In some but not all cases, this
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capability gates the use of later ISA vector instructions. The associated probe
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instruction is vor (vector logical or).
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Effect: Enables use of vector instructions but does not enable extensions added
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at specific ISA levels. However, disabling this capability disables a subset of
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vector extensions added at specific ISA levels even if they are otherwise
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enabled.
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=item 0x04
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Name: B<PPC_CRYPTO207>
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Meaning: Use instructions added in ISA level 2.07. The associated probe
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instruction instruction is vcipher (vector AES cipher round).
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Effect: Enables AES, SHA-2 sigma, and other ISA 2.07 instructions for AES, SHA-2,
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GHASH, and Poly1305.
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=item 0x08
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Name: B<PPC_FPU>
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Meaning: Use FPU instructions. The associated probe instruction is fmr (floating
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move register).
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Effect: Enables Poly1305 FPU implementation. The PPC_CRYPTO207 capability
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overrides this effect.
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=item 0x10
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Name: B<PPC_MADD300>
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Meaning: Use instructions added in ISA level 3.00. The associated probe
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instruction is maddhdu (multiply-add high doubleword unsigned).
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Effect: Enables use of the polynomial multiply and other ISA 3.00 instructions
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for AES-GCM, P-384, and P-521.
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=item 0x20
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Name: B<PPC_MFTB>
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Meaning: Use the mftb (move from time base) instruction. The associated probe
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instruction is mftb.
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Effect: Enables use of the mftb instruction to sample the lower 32 bits of the
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CPU time base register in order to acquire entropy. Considered obsolete. The
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PPC_MFSPR268 capability overrides this capability.
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=item 0x40
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Name: B<PPC_MFSPR268>
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Meaning: Use the mfspr (move from special purpose register) instruction to
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read SPR 268. The associated probe instruction is mfspr 268.
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Effect: Enables use of the mfspr instruction to sample the lower 32 bits of the
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CPU time base register from SPR 268, the TBL (time base lower) register, in order
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to acquire entropy.
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=item 0x80
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Name: B<PPC_BRD31>
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Meaning: Use instructions added in ISA level 3.1. The associated probe instruction
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is brd (byte-reverse doubleword).
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Effect: Enables use of ISA 3.1 instructions in ChaCha20.
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=back
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=head1 RETURN VALUES
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Not available.
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=head1 EXAMPLES
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Check currently detected capabilities:
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$ openssl info -cpusettings
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OPENSSL_ppccap=0x2E
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The detected capabilities in the above example indicate that PPC_MFTB, PPC_FPU,
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PPC_CRYPTO207, PPC_MFSPR268, and PPC_ALTIVEC are enabled.
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Disable all instruction set extensions:
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OPENSSL_ppccap=0x00
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Enable base AltiVec extensions:
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OPENSSL_ppccap=0x02
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=head1 COPYRIGHT
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Copyright 2025 The OpenSSL Project Authors. All Rights Reserved.
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Licensed under the Apache License 2.0 (the "License"). You may not use
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this file except in compliance with the License. You can obtain a copy
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in the file LICENSE in the source distribution or at
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L<https://www.openssl.org/source/license.html>.
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=cut
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