231 lines
11 KiB
C++
231 lines
11 KiB
C++
//===-- W65816ISelLowering.h - W65816 DAG Lowering Interface ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that W65816 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_W65816_W65816ISELLOWERING_H
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#define LLVM_LIB_TARGET_W65816_W65816ISELLOWERING_H
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#include "W65816.h"
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#include "llvm/CodeGen/TargetLowering.h"
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// W65816ISD::{Wrapper, CALL, RET_GLUE, ...} are defined by TableGen in
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// W65816GenSDNodeInfo.inc; that header is included transitively via
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// W65816SelectionDAGInfo.h.
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namespace llvm {
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class W65816Subtarget;
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class W65816TargetLowering : public TargetLowering {
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public:
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explicit W65816TargetLowering(const TargetMachine &TM,
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const W65816Subtarget &STI);
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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// Lock i16 shift amounts to i16 (not i32) even when i32 is a legal
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// type. Without this, the DAG combiner promotes i16 shift amounts
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// to i32 once i32 is registered as legal, leaving (sra i16, i32:K)
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// with no matching pattern. Only narrow when LHS is i16; leave i32
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// shifts (which go to libcall via LowerShift) alone.
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MVT getScalarShiftAmountTy(const DataLayout &DL,
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EVT LHSTy) const override {
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if (LHSTy == MVT::i16 || LHSTy == MVT::i8) return MVT::i16;
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return TargetLoweringBase::getScalarShiftAmountTy(DL, LHSTy);
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}
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// ptr32-mode hook: with patches/0007-targetlowering-virtual-
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// gettypeconversion making the base function virtual, this can be
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// overridden to force i64 to expand directly to i16 halves rather
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// than going through i32 (the next-smaller-legal type). Currently
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// not overridden — the override-calling-base passthrough caused
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// regressions in unrelated functions (likely due to subtle
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// de-virtualization changes when the function becomes virtual).
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// Future fix needs to test the override more carefully.
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const override;
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// The 65816 has no alignment requirement on memory access — any
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// address is fine. Telling LLVM this lets it emit single 16-bit
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// loads/stores even when the IR alignment is 1, instead of
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// synthesising the value from two byte loads + shl-or.
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
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Align Alignment = Align(1),
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MachineMemOperand::Flags Flags =
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MachineMemOperand::MONone,
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unsigned *Fast = nullptr) const override {
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if (Fast) *Fast = 1;
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return true;
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}
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// Disable LLVM's magic-constant expansion of sdiv/srem by power-of-2.
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// The default expansion generates BUILD_VECTOR (used as a "splat shifter"
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// intermediate) which we can't lower; without an override, every sdiv/srem
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// by a pow2 constant crashes ISel. Returning the original node leaves it
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// intact for the libcall lowering path (SDIV/SREM are LibCall in our
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// ctor — see setOperationAction calls above).
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SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
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SelectionDAG &DAG,
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SmallVectorImpl<SDNode *> &Created) const override {
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return SDValue(N, 0);
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}
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SDValue BuildSREMPow2(SDNode *N, const APInt &Divisor,
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SelectionDAG &DAG,
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SmallVectorImpl<SDNode *> &Created) const override {
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return SDValue(N, 0);
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}
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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// Inline-asm register constraints. Supports:
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// "a" / "{a}" — accumulator (A) — Acc16 (or Acc8 for i8 type)
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// "x" / "{x}" — index X — Idx16 (or Idx8)
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// "y" / "{y}" — index Y — Idx16 (or Idx8)
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// "r" — any allocatable register — Acc16 by default
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// Letting users name A/X/Y opens up direct toolbox-call sequences,
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// hand-written math kernels, and any other place where the back-end
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// doesn't already know to use a particular reg.
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint,
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MVT VT) const override;
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// Classify single-letter constraints 'a','x','y' as register-class
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// constraints so SelectionDAGBuilder routes them to the resolver
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// above rather than reporting "unknown asm constraint."
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ConstraintType getConstraintType(StringRef Constraint) const override {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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case 'a': case 'x': case 'y': case 'r':
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return C_RegisterClass;
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default: break;
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}
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}
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return TargetLowering::getConstraintType(Constraint);
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}
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// Force i32 / i64 shifts through a libcall (__ashlsi3 / __lshrsi3 /
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// __ashrsi3) instead of LLVM's default ExpandToParts strategy, which
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// emits an SHL_PARTS node we have no pattern for. ExpandToParts also
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// produces a long select-based sequence; the libcall is both smaller
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// and matches our existing libcall-based approach for i16 mul/div.
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ShiftLegalizationStrategy
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preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
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unsigned ExpansionFactor) const override {
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if (N->getValueType(0).getSizeInBits() > 16)
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return ShiftLegalizationStrategy::LowerToLibcall;
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return TargetLowering::preferredShiftLegalizationStrategy(DAG, N,
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ExpansionFactor);
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}
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// i16 MUL goes through __mulhi3 libcall. Tell the DAG combiner that
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// decomposing a constant multiply into shifts and adds is profitable:
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// a libcall is ~12 instructions, while `(mul x, 3)` -> `(add x, (shl
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// x, 1))` is 5. i32 stays libcall — the per-half shift+add+chain
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// expansion comes out larger than the __mulsi3 call.
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bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
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SDValue C) const override {
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return VT == MVT::i16;
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}
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// The DAG combiner has a transform `(trunc (shl X, K)) -> (shl (trunc X), K)`
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// gated on `isTypeDesirableForOp(SHL, NarrowVT)`. Our LowerShift expands
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// i8 SHL/SRL/SRA to `(trunc (shift (zext X), K))`; the combiner then
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// narrows it back to `(shift X, K)` of i8, which re-enters LowerShift —
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// an infinite loop that hangs `unsigned char x << 1` at -O1/-O2.
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// Return false for shifts on i8 to disable that narrowing combine and
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// keep the operation in i16 once we've widened it.
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bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override {
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if (VT == MVT::i8 &&
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(Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA))
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return false;
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return TargetLowering::isTypeDesirableForOp(Opc, VT);
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}
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// Disallow merging stores into wider ones. With ptr32 active and i32
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// a Custom-lowered op, the SDAG combiner's MergeConsecutiveStores
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// takes our LowerStore-split pair (2x i16 stores at &t and &t+2) and
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// merges them back into a single i32 store, which re-enters
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// LowerStore, splits again, and loops forever — observed as
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// "LLVM ERROR: out of memory" on `*t = K` for any K (including 0
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// when the SDAG state lets the combiner pick the merge ahead of any
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// STZ-pattern simplification). Anything wider than i16 has no
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// legal ptr-store pattern in our backend anyway, so merging into
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// wider VTs is purely counterproductive.
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bool canMergeStoresTo(unsigned AS, EVT MemVT,
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const MachineFunction &MF) const override {
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if (MemVT.isInteger() && MemVT.getSizeInBits() > 16)
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return false;
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return TargetLowering::canMergeStoresTo(AS, MemVT, MF);
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}
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private:
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBRIND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSignExtend(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDynamicStackalloc(SDValue Op, SelectionDAG &DAG) const;
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// Foundation hooks for ptr32 mode. In ptr16 mode (current default),
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// both return SDValue() so the legalizer falls through to the default
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// i16-pointer LDAptr/STAptr selection. When ptr32 mode is enabled
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// (PointerWidth=32 + Wide32 added as i32 reg class), they detect i32
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// addresses and wrap the load/store in W65816ISD::LD_PTR / ST_PTR /
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// STB_PTR so the [dp],Y inserter takes the bank byte from the
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// pointer's hi half instead of forcing 0.
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SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
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// ZERO/SIGN/ANY_EXTEND i16 -> i32 and TRUNCATE i32 -> i16 lowering
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// via REG_SEQUENCE / EXTRACT_SUBREG on the sub_lo/sub_hi indexes of
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// the Wide32 register class. Active once i32 is registered as a
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// legal type.
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SDValue LowerExtend(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerTruncate(SDValue Op, SelectionDAG &DAG) const;
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// SIGN_EXTEND_INREG i32 with inner type i1 / i8 / i16: sign-extend
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// the low N bits of the i32 input to fill all 32 bits. Splits to
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// (sext_inreg lo, innerVT) for the low half and SRA #15 of the
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// resulting i16 for the high half.
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SDValue LowerSignExtendInReg(SDValue Op, SelectionDAG &DAG) const;
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// ADD/SUB/AND/OR/XOR i32 split into per-half i16 ops. The carry-
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// chain ADDC/ADDE pseudos handle the cross-half link for ADD/SUB.
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SDValue LowerI32Bin(SDValue Op, SelectionDAG &DAG) const;
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// i32 ConstantNode: split into two i16 constants and REG_SEQUENCE.
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SDValue LowerI32Constant(SDValue Op, SelectionDAG &DAG) const;
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// i32 MUL: detect (zext i16 a) * (zext i16 b) — or operands with
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// provably-zero high 16 bits — and emit __umulhisi3 (16x16 -> 32)
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// instead of __mulsi3 (32x32 -> 32). Cuts ~30% off the canonical
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// sumSquares-style loop.
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SDValue LowerMUL_I32(SDValue Op, SelectionDAG &DAG) const;
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};
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} // namespace llvm
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#endif
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