245 lines
8.5 KiB
ArmAsm
245 lines
8.5 KiB
ArmAsm
; crt0 — C runtime startup for the W65816 backend.
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;
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; Entry point invoked by the loader (or the OMF dispatcher). Sets up
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; the processor mode the rest of the runtime expects, zeroes BSS,
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; calls main, and halts on return.
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;
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; Conventions:
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; - Native mode (E=0), 16-bit M and X (REP #$30) on entry to main.
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; - DP=0, DBR=0 — assumed by the C runtime.
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; - Linker-emitted symbols: __bss_start, __bss_end (16-bit addrs).
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.text
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.globl __start
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__start:
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; Disable IRQ first — the IIgs ROM hands a vsync IRQ on every frame,
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; and its handler runs in 8-bit M/X mode, corrupting our state if
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; we leave I clear. SEI is fine in either emulation or native
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; mode and is always 1 byte / 2 cycles.
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sei
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; Native mode + 16-bit registers.
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clc
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xce
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rep #0x30
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; Disable IIgs peripheral interrupt sources at the chip level —
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; SEI alone leaves the hardware lines asserted, and the IRQ trap
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; in ROM keeps re-firing if the source isn't quiesced. STZ
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; stores zero without going through A; in M=8 it stores 1 byte
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; (matching the 8-bit registers), so no LDA #0 prelude is needed.
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sep #0x20
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stz 0xc041 ; INTEN = 0 (clear AN3/mouse/0.25s/VBL/mouse-IRQ enables)
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stz 0xc023 ; VGCINT = 0 (clear external/1-sec/scan-line IRQ enables)
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stz 0xc032 ; SCANINT clear
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rep #0x20
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; Top-of-stack at $0FFF. Native-mode S is 16-bit, so we don't need
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; to stay in page 1. Soft-double frames can be ~170 bytes plus the
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; usual call-chain overhead — at $01FF stack growth wraps into the
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; direct page ($0000-$00FF) which holds our libcall scratch
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; ($E0-$F4) and IMG slots ($D0-$DE), corrupting them. $0FFF gives
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; ~3.5 KB of headroom and stays below the text base ($1000).
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lda #0x0fff
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tcs
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; Enable Language Card RAM at $D000-$FFFF for read+write. This
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; is 12KB (4KB at $D000-$DFFF in LC bank 1, plus 8KB at
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; $E000-$FFFF common LC area). The IIgs LC area defaults to
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; ROM-mapped; two reads of $C083 enable bank-1 RAM read AND
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; write for the whole $D000-$FFFF range. link816 may auto-
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; relocate BSS / heap into this area when text+rodata grows
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; past $BFFF — without this enable, writes drop on the floor
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; and reads return ROM bytes. The reads must be 8-bit (one
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; byte at a time) — a 16-bit M read at $C083 would also touch
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; $C084 (a different soft switch), wiping the LC enable.
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sep #0x20
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lda 0xc083
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lda 0xc083
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rep #0x20
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; Persistent "current data bank" byte at DP $BE. The LDAptr/
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; STAptr/STBptr inserters load this into $E2 before each [dp],Y
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; deref so pointer-deref lands in the user's bank, matching where
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; DBR-relative absolute stores go. Under MAME (no Loader), DBR=0
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; and PBR=0 here, so $BE=0 — equivalent to the prior STZ $E2
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; behavior. Under GS/OS Loader, crt0Gsos.s sets it to PBR.
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;
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; $BE chosen because it's outside both the libcall scratch range
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; ($E0..$FF used by libgcc.s for i64 ops) and the IMG slot range
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; ($C0..$DE). PHK pushes 1 byte; PLA in M=8 to pull just 1 byte.
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sep #0x20
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phk
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pla ; A's low byte = current PBR
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sta 0xbe ; persistent data bank
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stz 0xbf ; pad: `lda 0xbe` in 16-bit M loads $00PBR
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; — used by codegen for &symbol bank halves
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rep #0x20
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; Zero BSS. Up to 4 segments — linker emits __bss_seg{0..3}_lo16
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; / _bank / _size symbols. Segments with size=0 are skipped.
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; Each segment is cleared with DBR-relative STZ abs,X after
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; setting DBR to the segment's bank. Original DBR restored at
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; end via PLB.
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rep #0x10 ; ensure X is 16-bit
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phb ; save current DBR
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; ---- segment 0 ----
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; The `sep #0x20` that sets the segment's data bank also puts us in
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; M=8 for the whole store loop (X stays 16-bit), so we don't flip
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; SEP/REP per byte; each segment label below re-enters via `rep`.
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rep #0x20
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ldx #__bss_seg0_size
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beq .Lbss_seg1
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sep #0x20
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.a8 ; following lda #imm8 uses 1-byte immediate
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lda #__bss_seg0_bank
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pha
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plb
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ldx #0
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.Lbss_loop0:
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cpx #__bss_seg0_size
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bcs .Lbss_seg1
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stz __bss_seg0_lo16, x
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inx
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bra .Lbss_loop0
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.Lbss_seg1:
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; ---- segment 1 ----
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rep #0x20
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ldx #__bss_seg1_size
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beq .Lbss_seg2
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sep #0x20
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.a8 ; following lda #imm8 uses 1-byte immediate
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lda #__bss_seg1_bank
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pha
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plb
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ldx #0
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.Lbss_loop1:
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cpx #__bss_seg1_size
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bcs .Lbss_seg2
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stz __bss_seg1_lo16, x
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inx
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bra .Lbss_loop1
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.Lbss_seg2:
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; ---- segment 2 ----
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rep #0x20
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ldx #__bss_seg2_size
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beq .Lbss_seg3
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sep #0x20
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.a8 ; following lda #imm8 uses 1-byte immediate
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lda #__bss_seg2_bank
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pha
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plb
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ldx #0
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.Lbss_loop2:
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cpx #__bss_seg2_size
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bcs .Lbss_seg3
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stz __bss_seg2_lo16, x
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inx
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bra .Lbss_loop2
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.Lbss_seg3:
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; ---- segment 3 ----
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rep #0x20
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ldx #__bss_seg3_size
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beq .Lbss_done
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sep #0x20
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.a8 ; following lda #imm8 uses 1-byte immediate
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lda #__bss_seg3_bank
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pha
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plb
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ldx #0
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.Lbss_loop3:
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cpx #__bss_seg3_size
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bcs .Lbss_done
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stz __bss_seg3_lo16, x
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inx
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bra .Lbss_loop3
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.Lbss_done:
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rep #0x20 ; back to M=16 after the M=8 store loop
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plb ; restore caller's DBR
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; Run static constructors. The linker emits
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; __init_array_start / __init_array_end around the .init_array
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; section; under p:32:16 each entry is a 32-bit function pointer
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; (low 16 bits = function offset, high 16 bits = bank, 0 for our
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; single-bank programs). Walk in 4-byte stride and JSL each via
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; __jsl_indir using only the low half.
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rep #0x30 ; native, 16-bit M and X
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ldx #__init_array_start
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.Linit_loop:
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cpx #__init_array_end
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bcs .Linit_done
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; __jsl_indir does `JMP (__indirTarget)` — reads a 16-bit ptr
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; from __indirTarget and JMPs there. So __indirTarget must
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; hold the function pointer itself (NOT the address of the
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; init_array slot). Dereference the entry: ($E0)→A.
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stx 0xe0 ; entry addr -> DP scratch
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ldy #0
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lda (0xe0), y ; A = mem[X] (DP-indirect-Y, opcode 0xb1)
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sta 0xb8 ; __indirTarget pinned at DP $B8 (bank-0 fixed; see libgcc.s)
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phx ; preserve X across the call
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jsl __jsl_indir
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plx
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; Step by 4 bytes (sizeof(void*) under p:32:16).
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inx
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inx
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inx
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inx
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bra .Linit_loop
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.Linit_done:
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; Tool Locator init is the OS's job, not crt0's:
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; - GS/OS Loader (crt0Gsos.s path) pre-inits TL before transferring
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; control to __start. helloBeep proves this: it does `SysBeep`
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; (JSL $E10000 dispatch) with zero init in user code and works.
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; - GNO kernel (crt0Gno.s path) uses JSL $E10000 itself, so TL is
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; up before __start runs.
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; - Bare metal (this crt0.s): ROM pre-boot has already run
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; TLBootInit/MMBootInit; libc.c's iigsToolboxInit() does a per-
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; process TLStartUp + explicit SEI for clients of time()/clock().
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; Do NOT inline TLStartUp here — it CLI's internally, and the ROM
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; VBL handler runs in M=X=8 and would corrupt our in-progress
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; M=16 register state (the most plausible root of the earlier
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; attempt's "MAME segfault" mystery).
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; Programs that use per-process tools (MM/QD/EM/WM) must call
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; MMStartUp() and per-tool StartUps themselves — typically via
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; iigs/desktop.h's startdesk(640) helper.
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; Set DBR to the BSS bank before calling main. Without this, the
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; user has to manually switch the data bank register (with a
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; `pha;plb` inline-asm idiom) before doing absolute data
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; accesses. Calypsi's "small data model" assumes DBR is
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; pre-set; we now follow the same convention.
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;
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; Linker emits __bss_seg0_bank as the bank byte of the first
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; BSS segment (typically 2 with the default --bss-base 0x020000).
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; Programs that need bank-0 access (e.g., for $C0xx soft
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; switches) can use STA_Long or temporarily switch DBR back.
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sep #0x20
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.a8 ; following lda #imm8 uses 1-byte immediate
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lda #__bss_seg0_bank
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pha
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plb
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rep #0x20
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.a16 ; restore M=16 for the code that follows
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; Call main. Standard W65816 ABI: i16 first arg in A; we pass
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; nothing. After return, A holds the exit code.
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jsl main
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; Run global dtors registered via __cxa_atexit (LIFO order). No
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; OS exit on bare metal — they run before we spin. A holds main()'s
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; return; preserve it (harmless on bare metal but keeps the
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; convention uniform across crt0 variants).
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pha
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jsl __run_cxa_atexit
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pla
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; main returned. Bare metal has no OS to return to, so spin.
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; (Previously a BRK $00 here, but headless MAME mis-vectors BRK to
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; $0000 and wild-jumps, which reads as a crash. A tight loop is the
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; conventional bare-metal halt; IRQs are already masked above, so
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; this just idles.)
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.Lhalt:
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bra .Lhalt
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.size __start, . - __start
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