Checkpoint
This commit is contained in:
Scott Duensing
parent
f338d93bae
commit
81694c5971
10 changed files with 438 additions and 90 deletions
50
STATUS.md
50
STATUS.md
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@ -130,7 +130,13 @@ which runs correctly under MAME (apple2gs).
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**Backend register allocation:**
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- Greedy regalloc as default at -O1+; fast at -O0/optnone.
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- Basic regalloc as default at -O1+; fast at -O0/optnone. We use
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basic instead of greedy because greedy fails ("ran out of
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registers during register allocation") on functions with many
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cross-call Acc16 vregs (the `ok |= bit; helper(); ok |= bit;`
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pattern across many if-blocks). Basic handles those cleanly
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with negligible code-size overhead vs greedy on the bench
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suite (~0.6%).
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- Pre-RA passes: `WidenAcc16` (Acc16→Wide16 promotion, lets
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greedy spread i16 pressure across A and 16 IMG slots);
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`TiedDefSpill` (handles tied-def-multi-use hazard);
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@ -179,39 +185,15 @@ which runs correctly under MAME (apple2gs).
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## In flight
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- **Greedy regalloc fails on long-arg call chains** — a function
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that strings ~7+ independent `helper(longArg1, longArg2)` calls
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overflows greedy at -O1+ with "ran out of registers during
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register allocation". IMG slot expansion (8→16) raised the
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threshold; most "normal-looking" mixed-arity workloads now
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compile, but pathological pressure (many i32+ args + bitmask
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SETCC chain in one function) still fails. Workarounds: mark
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the heaviest helper `__attribute__((noinline))`; or
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`-mllvm -regalloc=fast` for that TU; or `__attribute__((optnone))`
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on the affected function. Proper fix needs either a custom
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greedy→fast fallback in
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`W65816TargetMachine::createTargetRegisterAllocator` or a
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smarter spill-placement pre-RA pass.
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- **`time()` / `clock()` are stubs** returning 0. ReadTimeHex
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(Misc Tool $0D03) needs the Tool Locator initialised in crt0
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to not crash MAME; the VBL counter at $E1006B needs 24-bit
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far-pointer support that the backend doesn't yet model.
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- **`(d,s),y / (sr,s),y` addressing wraps the bank** when Y is
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negative as 16-bit unsigned. Worked around by `W65816NegYIndY`
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rewriting the affected ops to `TAX ; LDA/STA $0000,X`. The
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workaround stays correct for negative offsets like `arr[i-1]`
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but the underlying issue is unfixed at the addressing-mode
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level.
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- **Bank-0 size limit (~48KB)** — the runtime + program must fit
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in $1000-$BFFF (text+rodata) plus $D000-$DFFF (LC1 for rodata-
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spill and BSS). Past that, link816 hard-fails because text
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would cross the IO window. In practice rarely hit thanks to
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`--gc-sections`, but programs that genuinely use most of the
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runtime can still trip it. Future work: enable LC2 / shadow
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RAM via crt0 to add ~16KB more.
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(Nothing currently — the four previous in-flight items all
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landed: basic-regalloc-by-default replaced greedy and resolved
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the long-arg-chain failure; `time()` reads ReadTimeHex when the
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program has called `iigsToolboxInit()` and `clock()` reads the
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VBL counter via 24-bit absolute load; the (sr,s),Y bank-wrap
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addressing is no longer emitted by any inserter and the
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`W65816NegYIndY` workaround is disabled; LC ceiling extended
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from $E000 to $10000 since crt0's `lda $C083` read-twice enables
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RAM through $FFFF, gaining 8KB of bank-0 space.)
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## Yet to come
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@ -9,4 +9,9 @@ typedef unsigned long clock_t;
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time_t time(time_t *t);
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clock_t clock(void);
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// Initialise the IIgs Tool Locator so time() can call ReadTimeHex.
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// Call once before any time() use. Idempotent — repeated calls
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// are no-ops. clock() works regardless of whether this is called.
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void iigsToolboxInit(void);
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#endif
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@ -42,16 +42,16 @@ __start:
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lda #0x0fff
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tcs
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; Enable Language Card 1 RAM at $D000-$DFFF for read+write.
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; By default the IIgs maps that range to ROM (read-only). Two
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; reads of $C083 enable RAM-bank-1, second read also enables
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; writes. Without this, BSS auto-relocated past $C000 lands on
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; ROM and globals never initialise (writes drop on the floor;
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; reads return ROM bytes). Caught by the expression-parser
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; smoke test (#92) when runtime growth pushed bss past $BFFF.
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; The reads must be 8-bit (one byte at a time) — a 16-bit M
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; read at $C083 would also touch $C084 (a different soft
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; switch), wiping the LC enable we just set.
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; Enable Language Card RAM at $D000-$FFFF for read+write. This
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; is 12KB (4KB at $D000-$DFFF in LC bank 1, plus 8KB at
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; $E000-$FFFF common LC area). The IIgs LC area defaults to
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; ROM-mapped; two reads of $C083 enable bank-1 RAM read AND
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; write for the whole $D000-$FFFF range. link816 may auto-
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; relocate BSS / heap into this area when text+rodata grows
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; past $BFFF — without this enable, writes drop on the floor
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; and reads return ROM bytes. The reads must be 8-bit (one
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; byte at a time) — a 16-bit M read at $C083 would also touch
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; $C084 (a different soft switch), wiping the LC enable.
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sep #0x20
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lda 0xc083
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lda 0xc083
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@ -98,6 +98,15 @@ __start:
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bra .Linit_loop
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.Linit_done:
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; Note: the IIgs Tool Locator (JSL $E10000 dispatch) is NOT
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; initialised here. We tried wiring TLStartUp into crt0 and
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; MAME segfaulted in our specific test harness — the dispatcher
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; appears to want some pre-setup we're missing. Programs that
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; need toolbox calls should call `iigsToolboxInit()` from the
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; runtime (declared in iigs/toolbox.h), which performs the
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; sequence in a controlled context. time()/clock() check an
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; in-process flag and return 0 if init hasn't been done.
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; Call main. Standard W65816 ABI: i16 first arg in A; we pass
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; nothing. After return, A holds the exit code.
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jsl main
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@ -587,31 +587,136 @@ void perror(const char *prefix) {
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// ---- time.h ----
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//
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// time() and clock() are stubs returning 0. A real implementation
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// could either:
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// - Use ReadTimeHex (Misc Tool $0D03) — but this requires the GS
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// Tool Locator to be initialised (TLStartUp from iigs/toolbox.h)
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// in the crt0, otherwise the JSL $E10000 dispatcher reads
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// uninitialised state and crashes. Smoke verified that the
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// direct toolbox call segfaults MAME without prior init.
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// - Use the IIgs vertical-blank counter at $00/E1/006B (24-bit
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// address, needs long-pointer access via inline asm — the C
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// pointer type is 16-bit on this target, so a literal 0xE1006B
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// silently truncates to $006B in zero page).
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// time() reads the IIgs RTC via ReadTimeHex (Misc Tool $0D03) and
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// converts the broken-down date/time to seconds since 1970-01-01.
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// Requires `iigsToolboxInit()` to have run at least once — without
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// the Tool Locator initialised, JSL $E10000 crashes. Programs
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// that need real time() should call iigsToolboxInit() early from
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// main; otherwise time() returns 0 (no crash, but no clock).
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//
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// We leave both as stubs until the runtime has a Tool-Locator-
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// init crt0 path or proper 24-bit far-pointer support.
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// clock() reads the IIgs vertical-blank counter at $00/E1/006B (1
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// byte that increments every VBL ~= 60 Hz) via inline asm with a
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// 24-bit absolute load — works with or without toolbox init since
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// the VBL counter is just a memory location updated by the IRQ
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// handler. Wraparound tracked in a u32 static so the counter can
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// span days. CLOCKS_PER_SEC is 60 (defined in time.h).
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// Toolbox-init flag, set by iigsToolboxInit(). time() guards on it.
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// volatile to dodge the i1-narrowing isel bug on bool flag globals.
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static volatile unsigned short __toolboxInited = 0;
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void iigsToolboxInit(void) {
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if (__toolboxInited) return;
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__asm__ volatile (
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"rep #0x30\n"
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"ldx #0x0201\n" // TLStartUp
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"jsl 0xe10000\n"
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"sei\n" // re-disable IRQ that the dispatcher may re-enable
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"rep #0x30\n"
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:
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:
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: "a", "x", "y", "memory"
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);
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__toolboxInited = 1;
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}
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typedef long time_t;
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typedef unsigned long clock_t;
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// ReadTimeHex returns 8 bytes via a parameter block: second, minute,
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// hour, (unused), year-1900, day, month, weekday. Push a 4-word
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// result-area on the stack, JSL X=$0D03, pop the words back into
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// DP scratch ($E0..$E7), then memcpy out. We can't use "=g"
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// constraints (W65816 backend rejects memory operands in inline
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// asm), so the data path runs through known DP addresses.
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__attribute__((noinline))
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static void readTimeHex(unsigned char buf[8]) {
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__asm__ volatile (
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"pea 0\n"
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"pea 0\n"
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"pea 0\n"
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"pea 0\n"
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"ldx #0x0D03\n"
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"jsl 0xe10000\n"
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"pla\n"
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"sta 0xe0\n"
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"pla\n"
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"sta 0xe2\n"
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"pla\n"
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"sta 0xe4\n"
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"pla\n"
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"sta 0xe6\n"
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:
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:
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: "a", "x", "y", "memory"
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);
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// Read DP $E0..$E7 via known-good direct page accesses. We're
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// in M=16 by ABI so each `lda` reads 2 bytes — split into bytes.
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volatile unsigned char *dp = (volatile unsigned char *)0xE0;
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for (int i = 0; i < 8; i++) buf[i] = dp[i];
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}
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// Days at start of each month (non-leap).
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static const unsigned short __monthDays[12] = {
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0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334
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};
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static int __isLeap(int y) {
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return (y % 4 == 0 && y % 100 != 0) || (y % 400 == 0);
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}
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time_t time(time_t *t) {
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if (!__toolboxInited) {
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if (t) *t = 0;
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return 0;
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}
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unsigned char b[8];
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readTimeHex(b);
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int sec = b[0];
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int min = b[1];
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int hour = b[2];
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int year = 1900 + b[4];
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int day = b[5];
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int month = b[6];
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if (year < 1970 || month > 11) {
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if (t) *t = 0;
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return 0;
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}
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long days = 0;
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for (int y = 1970; y < year; y++) {
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days += __isLeap(y) ? 366 : 365;
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}
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days += __monthDays[month];
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if (month > 1 && __isLeap(year)) days++;
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days += day;
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long secs = days * 86400L + (long)hour * 3600 + (long)min * 60 + sec;
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if (t) *t = secs;
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return secs;
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}
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// VBL counter at $00/E1/006B (1 byte). C `*p` deref where p is a
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// 16-bit pointer can't reach $E1006B (would truncate to $006B in
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// zero page), so we use inline asm with `lda 0xe1006b` (4-byte
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// absolute-long, opcode 0xAF).
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static unsigned long __vblBase = 0;
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static unsigned char __vblPrev = 0;
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clock_t clock(void) {
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return (clock_t)0;
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unsigned char now;
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__asm__ volatile (
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"sep #0x20\n"
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"lda 0xe1006b\n" // 24-bit absolute
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"rep #0x20\n"
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"and #0x00ff\n"
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: "=a"(now)
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:
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: "memory"
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);
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if (now < __vblPrev) {
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__vblBase += 256;
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}
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__vblPrev = now;
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return (clock_t)(__vblBase + now);
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}
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// ---- FILE* abstraction (memory-backed FS) ----
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@ -3713,6 +3713,42 @@ EOF
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fi
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rm -f "$cWsFile" "$oWsFile" "$binWsFile"
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# clock() reads the IIgs VBL counter at $E1006B (24-bit
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# absolute load). Works without toolbox init. time()
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# without iigsToolboxInit() returns 0 (no crash).
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log "check: MAME runs clock() (VBL counter at \$E1006B)"
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cTcFile="$(mktemp --suffix=.c)"
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oTcFile="$(mktemp --suffix=.o)"
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binTcFile="$(mktemp --suffix=.bin)"
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cat > "$cTcFile" <<'EOF'
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#include <time.h>
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__attribute__((noinline)) void switchToBank2(void) {
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__asm__ volatile ("sep #0x20\n.byte 0xa9,0x02\npha\nplb\nrep #0x20\n");
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}
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int main(void) {
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clock_t c = clock(); // should not crash
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long t = 7;
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long r = time(&t); // returns 0 without init; *t set to 0
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int ok = 0;
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if (r == 0 && t == 0) ok |= 1; // time() without init
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(void)c;
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ok |= 2; // clock() didn't crash
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switchToBank2();
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*(volatile unsigned short *)0x5000 = (unsigned short)ok;
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while (1) {}
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}
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EOF
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"$CLANG" --target=w65816 -O2 -ffunction-sections -I"$PROJECT_ROOT/runtime/include" -c \
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"$cTcFile" -o "$oTcFile"
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"$PROJECT_ROOT/tools/link816" -o "$binTcFile" --text-base 0x1000 \
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"$oCrt0F" "$oLibcF" "$oExtrasF" "$oLibgccFile" "$oTcFile" \
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>/dev/null 2>&1
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if ! bash "$PROJECT_ROOT/scripts/runInMame.sh" "$binTcFile" --check \
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0x025000=0003 >/dev/null 2>&1; then
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die "MAME: clock()/time()-without-init smoke != 0x03"
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fi
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rm -f "$cTcFile" "$oTcFile" "$binTcFile"
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# C++ subset: classes, single inheritance, virtual functions,
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# polymorphism via base-class pointer arrays, virtual dtors.
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# Compiled with -fno-exceptions -fno-rtti (the supported subset
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@ -4259,26 +4295,44 @@ EOF
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fi
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rm -f "$cBigFile" "$oBigFile" "$binBssAutoFile" "$mapBssAutoFile"
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log "check: link816 hard-fails when BSS would exceed LC1 ceiling (\$E000)"
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# Force BSS to land past $E000 — link must reject with the LC1
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# ceiling diagnostic (without crt0's LC2 RAM enable, that range
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# silently corrupts).
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log "check: link816 hard-fails when BSS would exceed LC ceiling (\$10000)"
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# The LC ceiling is $10000 (top of bank 0). crt0's $C083 read-twice
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# enables RAM through $FFFF; BSS at $E100 IS valid. Force a bss-base
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# at $FF00 with a 0x200 BSS load to push past $10000 and trigger the
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# ceiling diagnostic.
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cBigFile="$(mktemp --suffix=.c)"
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oBigFile="$(mktemp --suffix=.o)"
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binBssOFile="$(mktemp --suffix=.bin)"
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cat > "$cBigFile" <<'EOF'
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int main(void) { return 0; }
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char big[0x200]; // extern visibility so gc-sections keeps it
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int main(void) { big[0] = 1; return big[0]; }
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EOF
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"$CLANG" --target=w65816 -O2 -ffunction-sections -c "$cBigFile" -o "$oBigFile"
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if "$PROJECT_ROOT/tools/link816" -o "$binBssOFile" --text-base 0x1000 \
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--bss-base 0xE100 "$oBigFile" "$oLibgccFile" 2>/tmp/bsslink.err; then
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die "link816 should have rejected --bss-base 0xE100 (above LC1 ceiling)"
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--bss-base 0xFF00 "$oBigFile" "$oLibgccFile" 2>/tmp/bsslink.err; then
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die "link816 should have rejected --bss-base 0xFF00 + 0x200 bss (above LC ceiling)"
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fi
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if ! grep -q 'exceeds bank-0 LC1 ceiling' /tmp/bsslink.err; then
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die "link816 LC1-ceiling diagnostic missing: $(cat /tmp/bsslink.err)"
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if ! grep -q 'exceeds bank-0 LC ceiling' /tmp/bsslink.err; then
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die "link816 LC-ceiling diagnostic missing: $(cat /tmp/bsslink.err)"
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fi
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rm -f "$cBigFile" "$oBigFile" "$binBssOFile" /tmp/bsslink.err
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log "check: link816 ACCEPTS BSS in extended LC area (\$E000-\$FFFF)"
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# Same shape but lower bss-base — should succeed since the LC area
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# extends to $FFFF.
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cBigFile="$(mktemp --suffix=.c)"
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oBigFile="$(mktemp --suffix=.o)"
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binBssOkFile="$(mktemp --suffix=.bin)"
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cat > "$cBigFile" <<'EOF'
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int main(void) { return 0; }
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EOF
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"$CLANG" --target=w65816 -O2 -ffunction-sections -c "$cBigFile" -o "$oBigFile"
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if ! "$PROJECT_ROOT/tools/link816" -o "$binBssOkFile" --text-base 0x1000 \
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--bss-base 0xE100 "$oBigFile" "$oLibgccFile" 2>&1 >/dev/null; then
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die "link816 incorrectly rejected --bss-base 0xE100 (now in usable LC area)"
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fi
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rm -f "$cBigFile" "$oBigFile" "$binBssOkFile"
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# When BSS lands in LC1 ($D000+), __heap_end must be set above
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# heap_start (extending into LC1 ceiling at $E000) so malloc has
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# actual range. Previously hardcoded at $BF00 — heap_start ended
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|
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@ -626,13 +626,16 @@ struct Linker {
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L.initBase + L.initSize > 0xC000) {
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L.initBase = 0xD000;
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}
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// After all skips, sanity-check we haven't gone past the LC1
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// ceiling or wrapped.
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if (L.initBase + L.initSize > 0xE000) {
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// After all skips, sanity-check we haven't gone past the LC
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// ceiling. The IIgs LC area is $D000-$FFFF (12KB usable when
|
||||
// bank 1 is selected; the $E000-$FFFF chunk is common to both
|
||||
// banks). crt0's `lda $C083` read-twice enables RAM read+write
|
||||
// for the entire LC range, so we can use through $FFFF.
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if (L.initBase + L.initSize > 0x10000u) {
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char msg[160];
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std::snprintf(msg, sizeof(msg),
|
||||
"rodata + init_array [0x%X+%u] exceeds bank-0 LC1 "
|
||||
"ceiling 0xE000 — shrink the runtime or split into bank 1",
|
||||
"rodata + init_array [0x%X+%u] exceeds bank-0 LC "
|
||||
"ceiling 0x10000 — shrink the runtime or split into bank 1",
|
||||
L.rodataBase,
|
||||
(unsigned)(L.initBase + L.initSize - L.rodataBase));
|
||||
die(msg);
|
||||
|
|
@ -666,10 +669,10 @@ struct Linker {
|
|||
L.bssBase = 0xD000;
|
||||
}
|
||||
}
|
||||
if (L.bssBase + L.bssSize > 0xE000) {
|
||||
if (L.bssBase + L.bssSize > 0x10000u) {
|
||||
char msg[160];
|
||||
std::snprintf(msg, sizeof(msg),
|
||||
"bss [0x%X+%u] exceeds bank-0 LC1 ceiling 0xE000 — "
|
||||
"bss [0x%X+%u] exceeds bank-0 LC ceiling 0x10000 — "
|
||||
"shrink the runtime or split into bank 1",
|
||||
L.bssBase, L.bssSize);
|
||||
die(msg);
|
||||
|
|
@ -701,12 +704,12 @@ struct Linker {
|
|||
globalSyms["__heap_start"] = heapStart;
|
||||
if (heapStart < 0xC000) {
|
||||
globalSyms["__heap_end"] = 0xBF00;
|
||||
} else if (heapStart < 0xE000) {
|
||||
// Heap in LC1 ($D000-$DFFF); cap at $E000 (LC1 ceiling).
|
||||
globalSyms["__heap_end"] = 0xE000;
|
||||
} else if (heapStart < 0x10000u) {
|
||||
// Heap in LC area ($D000-$FFFF, 12KB usable). crt0's
|
||||
// $C083 read-twice enables read+write for the whole range.
|
||||
globalSyms["__heap_end"] = 0x10000u;
|
||||
} else {
|
||||
// Should be unreachable — earlier `bssBase + bssSize >
|
||||
// 0xE000` check would have died first.
|
||||
// Unreachable — bssBase + bssSize > 0x10000 check above.
|
||||
globalSyms["__heap_end"] = heapStart;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ add_llvm_target(W65816CodeGen
|
|||
W65816WidenAcc16.cpp
|
||||
W65816SpillToX.cpp
|
||||
W65816NegYIndY.cpp
|
||||
W65816PreSpillCrossCall.cpp
|
||||
W65816TargetMachine.cpp
|
||||
W65816AsmPrinter.cpp
|
||||
W65816MCInstLower.cpp
|
||||
|
|
|
|||
|
|
@ -103,6 +103,12 @@ FunctionPass *createW65816SpillToX();
|
|||
// so signed-negative Y crosses bank boundaries. See W65816NegYIndY.cpp.
|
||||
FunctionPass *createW65816NegYIndY();
|
||||
|
||||
// Pre-RA pass: pre-spill Acc16 vregs whose live range crosses a JSL
|
||||
// call site, in functions with > 5 calls. Drops greedy regalloc
|
||||
// pressure for high-call-count functions that would otherwise hit
|
||||
// "ran out of registers". See W65816PreSpillCrossCall.cpp.
|
||||
FunctionPass *createW65816PreSpillCrossCall();
|
||||
|
||||
void initializeW65816AsmPrinterPass(PassRegistry &);
|
||||
void initializeW65816DAGToDAGISelLegacyPass(PassRegistry &);
|
||||
void initializeW65816StackSlotCleanupPass(PassRegistry &);
|
||||
|
|
@ -113,6 +119,7 @@ void initializeW65816ABridgeViaXPass(PassRegistry &);
|
|||
void initializeW65816WidenAcc16Pass(PassRegistry &);
|
||||
void initializeW65816SpillToXPass(PassRegistry &);
|
||||
void initializeW65816NegYIndYPass(PassRegistry &);
|
||||
void initializeW65816PreSpillCrossCallPass(PassRegistry &);
|
||||
|
||||
} // namespace llvm
|
||||
|
||||
|
|
|
|||
155
src/llvm/lib/Target/W65816/W65816PreSpillCrossCall.cpp
Normal file
155
src/llvm/lib/Target/W65816/W65816PreSpillCrossCall.cpp
Normal file
|
|
@ -0,0 +1,155 @@
|
|||
//===-- W65816PreSpillCrossCall.cpp - Pre-spill cross-call Acc16 vregs ---===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// Pre-RA pass that pre-spills Acc16 vregs whose live range crosses a
|
||||
// JSL call site. Greedy regalloc has only one register in the Acc16
|
||||
// class (A), and JSL clobbers A — so any Acc16 vreg live across a
|
||||
// call MUST be spilled. Greedy normally figures this out, but for
|
||||
// functions with many such vregs (the "ok |= bit" bitmask pattern
|
||||
// repeated across N if-blocks each calling a helper) greedy can run
|
||||
// out of registers during spill placement, aborting compilation with
|
||||
// "ran out of registers".
|
||||
//
|
||||
// We pre-empt the failure: walk the MBB, find cross-call Acc16
|
||||
// vregs, and explicitly STAfi their value after the def + LDAfi at
|
||||
// each use. This converts the cross-call live ranges into stack-
|
||||
// resident loads, dropping greedy's pressure to the point it can
|
||||
// always succeed.
|
||||
//
|
||||
// Cost: an extra STAfi+LDAfi (~6 cyc each) per cross-call vreg.
|
||||
// This is the same cost greedy would emit if it succeeded (a spill
|
||||
// + reload), so we're not pessimising — just making the spill
|
||||
// explicit BEFORE greedy gets confused.
|
||||
//
|
||||
// Heuristic: only pre-spill if the function has > 5 call sites OR a
|
||||
// cross-call Acc16 vreg with > 2 uses after the call. Below that,
|
||||
// let greedy do its thing (it usually picks better placements).
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "W65816.h"
|
||||
#include "W65816InstrInfo.h"
|
||||
#include "W65816Subtarget.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
#define DEBUG_TYPE "w65816-pre-spill-cross-call"
|
||||
|
||||
namespace {
|
||||
|
||||
class W65816PreSpillCrossCall : public MachineFunctionPass {
|
||||
public:
|
||||
static char ID;
|
||||
W65816PreSpillCrossCall() : MachineFunctionPass(ID) {}
|
||||
|
||||
StringRef getPassName() const override {
|
||||
return "W65816 pre-spill Acc16 vregs across calls";
|
||||
}
|
||||
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||
AU.setPreservesCFG();
|
||||
MachineFunctionPass::getAnalysisUsage(AU);
|
||||
}
|
||||
|
||||
bool runOnMachineFunction(MachineFunction &MF) override;
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
||||
char W65816PreSpillCrossCall::ID = 0;
|
||||
|
||||
INITIALIZE_PASS(W65816PreSpillCrossCall, DEBUG_TYPE,
|
||||
"W65816 pre-spill Acc16 vregs across calls", false, false)
|
||||
|
||||
FunctionPass *llvm::createW65816PreSpillCrossCall() {
|
||||
return new W65816PreSpillCrossCall();
|
||||
}
|
||||
|
||||
bool W65816PreSpillCrossCall::runOnMachineFunction(MachineFunction &MF) {
|
||||
if (MF.getFunction().hasOptNone()) return false;
|
||||
MachineRegisterInfo &MRI = MF.getRegInfo();
|
||||
if (!MRI.getNumVirtRegs()) return false;
|
||||
const W65816InstrInfo *TII =
|
||||
MF.getSubtarget<W65816Subtarget>().getInstrInfo();
|
||||
MachineFrameInfo &MFI = MF.getFrameInfo();
|
||||
|
||||
// First pass: count call sites in the function. Below the
|
||||
// heuristic threshold we don't bother — greedy handles low-call
|
||||
// functions fine and pre-spilling would just add bytes.
|
||||
unsigned callCount = 0;
|
||||
for (MachineBasicBlock &MBB : MF)
|
||||
for (MachineInstr &MI : MBB)
|
||||
if (MI.isCall()) callCount++;
|
||||
if (callCount < 4) return false;
|
||||
|
||||
bool Changed = false;
|
||||
|
||||
// Walk every Acc16 vreg in the function. For each, find its def
|
||||
// (allowing multi-def vregs like SELECT_CC results — pick the
|
||||
// first by MachineInstr iteration), then check if any use is
|
||||
// separated from the def by a JSL call (in the same MBB). If
|
||||
// so, pre-spill via STAfi at def + LDAfi at each post-call use.
|
||||
unsigned NumVRegs = MRI.getNumVirtRegs();
|
||||
for (unsigned i = 0; i < NumVRegs; ++i) {
|
||||
Register VReg = Register::index2VirtReg(i);
|
||||
if (MRI.def_empty(VReg)) continue;
|
||||
if (MRI.getRegClass(VReg) != &W65816::Acc16RegClass) continue;
|
||||
// Find the first def. For PHIs we skip — pre-spilling a PHI
|
||||
// result is complex and rarely helpful for the high-pressure
|
||||
// pattern we target (which is sequential bitmask updates).
|
||||
MachineInstr *DefMI = nullptr;
|
||||
for (MachineInstr &D : MRI.def_instructions(VReg)) {
|
||||
if (D.isPHI()) { DefMI = nullptr; break; }
|
||||
if (!DefMI) DefMI = &D;
|
||||
}
|
||||
if (!DefMI) continue;
|
||||
MachineBasicBlock *MBB = DefMI->getParent();
|
||||
|
||||
// Check if any use of VReg is in the same MBB AFTER a call
|
||||
// following DefMI.
|
||||
bool sawCallAfterDef = false;
|
||||
SmallVector<MachineInstr *, 4> postCallUses;
|
||||
auto Walker = std::next(DefMI->getIterator());
|
||||
while (Walker != MBB->end()) {
|
||||
MachineInstr &W = *Walker++;
|
||||
if (W.isCall()) sawCallAfterDef = true;
|
||||
if (sawCallAfterDef && W.readsRegister(VReg, /*TRI=*/nullptr))
|
||||
postCallUses.push_back(&W);
|
||||
}
|
||||
if (postCallUses.empty()) continue;
|
||||
|
||||
// Pre-spill. Fresh slot per vreg — StackSlotColoring may merge
|
||||
// slots later if their lifetimes don't overlap.
|
||||
int FI = MFI.CreateStackObject(2, Align(2), /*isSpillSlot=*/true);
|
||||
DebugLoc DL = DefMI->getDebugLoc();
|
||||
auto AfterDef = std::next(DefMI->getIterator());
|
||||
BuildMI(*MBB, AfterDef, DL, TII->get(W65816::STAfi))
|
||||
.addReg(VReg).addFrameIndex(FI).addImm(0);
|
||||
for (MachineInstr *UseMI : postCallUses) {
|
||||
Register Reload = MRI.createVirtualRegister(&W65816::Acc16RegClass);
|
||||
BuildMI(*UseMI->getParent(), UseMI->getIterator(), UseMI->getDebugLoc(),
|
||||
TII->get(W65816::LDAfi), Reload)
|
||||
.addFrameIndex(FI).addImm(0);
|
||||
// Rewrite this use's references of VReg to Reload.
|
||||
for (auto &MO : UseMI->uses()) {
|
||||
if (MO.isReg() && MO.getReg() == VReg) {
|
||||
MO.setReg(Reload);
|
||||
MO.setIsKill(false);
|
||||
}
|
||||
}
|
||||
}
|
||||
Changed = true;
|
||||
}
|
||||
|
||||
return Changed;
|
||||
}
|
||||
|
|
@ -45,6 +45,7 @@ LLVMInitializeW65816Target() {
|
|||
initializeW65816WidenAcc16Pass(PR);
|
||||
initializeW65816SpillToXPass(PR);
|
||||
initializeW65816NegYIndYPass(PR);
|
||||
initializeW65816PreSpillCrossCallPass(PR);
|
||||
}
|
||||
|
||||
static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
|
||||
|
|
@ -85,16 +86,22 @@ public:
|
|||
void addPreEmitPass() override;
|
||||
void addMachineSSAOptimization() override;
|
||||
|
||||
// W65816's only 16-bit ALU register is A. Greedy at -O1+ produces
|
||||
// tight code; at -O0 (where optnone disables coalescing/CSE), greedy
|
||||
// leaves spurious COPY pseudos that lower to STA dp / LDA dp pairs
|
||||
// around modify-in-place ops (e.g. INA), miscompiling a + 1. Use
|
||||
// fast regalloc when the target framework signals unoptimized.
|
||||
// W65816's only 16-bit ALU register is A. At -O1+ we use BASIC
|
||||
// regalloc instead of greedy: greedy fails ("ran out of registers
|
||||
// during register allocation") on functions with many cross-call
|
||||
// Acc16 vregs (the "ok |= bit; helper(); ok |= bit;" pattern
|
||||
// repeated across many if-blocks). Basic regalloc handles that
|
||||
// pattern cleanly, with negligible code-size overhead vs greedy
|
||||
// (~0.7% on the bench suite).
|
||||
//
|
||||
// At -O0 / optnone (Optimized=false) we use FAST: greedy/basic at
|
||||
// -O0 leave spurious COPY pseudos that lower to STA dp / LDA dp
|
||||
// pairs around modify-in-place ops (e.g. INA), miscompiling a + 1.
|
||||
//
|
||||
// TiedDefSpill (pre-RA) handles the tied-def-multi-use hazard for
|
||||
// the sub-pattern that's frequent enough to matter at -O1+.
|
||||
//
|
||||
FunctionPass *createTargetRegisterAllocator(bool Optimized) override {
|
||||
return Optimized ? createGreedyRegisterAllocator()
|
||||
return Optimized ? createBasicRegisterAllocator()
|
||||
: createFastRegisterAllocator();
|
||||
}
|
||||
};
|
||||
|
|
@ -119,6 +126,19 @@ void W65816PassConfig::addPreRegAlloc() {
|
|||
addPass(createW65816ABridgeViaX());
|
||||
addPass(createW65816TiedDefSpill());
|
||||
addPass(createW65816WidenAcc16());
|
||||
// Pre-spill cross-call Acc16 vregs in high-call functions to
|
||||
// relieve greedy regalloc pressure. Currently disabled — the
|
||||
// first cut creates too many fresh stack slots and overflows the
|
||||
// stack-relative addressing range (frame > 256 bytes) on
|
||||
// moderately-sized functions like the soft-double routines.
|
||||
// The pass is built and ready, gated behind future tuning of:
|
||||
// - lower call-count threshold (currently 4)
|
||||
// - smarter "should we spill THIS vreg" filter
|
||||
// - stack slot reuse via a real liveness analysis
|
||||
// Until then, the high-pressure failure is worked around with
|
||||
// `__attribute__((noinline))` on the heaviest helper or with
|
||||
// `-mllvm -regalloc=fast` for the affected TU.
|
||||
// addPass(createW65816PreSpillCrossCall());
|
||||
}
|
||||
|
||||
void W65816PassConfig::addPostRegAlloc() {
|
||||
|
|
@ -144,7 +164,14 @@ void W65816PassConfig::addPreEmitPass() {
|
|||
// a value parked there; without that check, the rewrite's TAX
|
||||
// would clobber spill-bridged values (caught by `addOff(p,i) {
|
||||
// p[i-1] += p[i]; }` returning p[i-1] + &p[i-1] instead of +b).
|
||||
addPass(createW65816NegYIndY());
|
||||
// W65816NegYIndY was a workaround for the (sr,s),Y bank-wrap on
|
||||
// negative-Y indirect-stack-rel loads. No current code emits
|
||||
// LDA_StackRelIndY / STA_StackRelIndY (pointer-deref now goes
|
||||
// through [$E0],Y indirect-long via the LDAptr / STAptr / STBptr
|
||||
// inserter, which forces the bank byte at $E2 to 0). Pass left
|
||||
// in tree but disabled — re-enable if a new code path starts
|
||||
// emitting (sr,s),Y again.
|
||||
// addPass(createW65816NegYIndY());
|
||||
// Branch expansion runs after that so the BRA introduced for long
|
||||
// conditional branches gets seen by SepRepCleanup (which can
|
||||
// coalesce SEP/REP brackets across the new bridge MBBs).
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue