Checkpoint
This commit is contained in:
Scott Duensing
parent
465f8ba947
commit
0210b06a5e
24 changed files with 875 additions and 109 deletions
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@ -7,7 +7,7 @@ index 8837d2f91..920b8ac8e 100644
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case Triple::msp430:
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return "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16";
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+ case Triple::w65816:
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+ return "e-m:e-p:16:16-i16:16-i32:16-i64:16-f32:16-f64:16-n8:16-S16";
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+ return "e-m:e-p:32:16-i16:16-i32:16-i64:16-f32:16-f64:16-n8:16-S16";
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case Triple::ppc:
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case Triple::ppcle:
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case Triple::ppc64:
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@ -91,8 +91,10 @@ __start:
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; Run static constructors. The linker emits
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; __init_array_start / __init_array_end around the .init_array
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; section; each entry is a 16-bit function pointer. Walk and
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; JSL each via __jsl_indir.
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; section; under p:32:16 each entry is a 32-bit function pointer
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; (low 16 bits = function offset, high 16 bits = bank, 0 for our
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; single-bank programs). Walk in 4-byte stride and JSL each via
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; __jsl_indir using only the low half.
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rep #0x30 ; native, 16-bit M and X
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ldx #__init_array_start
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.Linit_loop:
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@ -105,10 +107,13 @@ __start:
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stx 0xe0 ; entry addr -> DP scratch
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ldy #0
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lda (0xe0), y ; A = mem[X] (DP-indirect-Y, opcode 0xb1)
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sta __indirTarget ; __indirTarget = function pointer
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sta __indirTarget ; __indirTarget = function pointer (lo16)
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phx ; preserve X across the call
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jsl __jsl_indir
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plx
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; Step by 4 bytes (sizeof(void*) under p:32:16).
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inx
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inx
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inx
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inx
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bra .Linit_loop
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@ -91,6 +91,9 @@ __start:
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phx
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jsl __jsl_indir
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plx
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; Step by 4 bytes (sizeof(void*) under p:32:16).
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inx
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inx
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inx
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inx
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bra .Linit_loop
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@ -1009,6 +1009,28 @@ int atexit(AtexitFn fn) {
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// Returns NULL if no registration matches `path` (or the requested
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// mode isn't compatible with the registration's writable flag).
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__attribute__((noinline))
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static void initFileMem(FILE *f, const MfsEntry *reg, int wantWrite) {
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f->kind = FILE_KIND_MEM;
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f->writable = (u8)(wantWrite ? 1 : 0);
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f->eof = 0;
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f->err = 0;
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f->buf = reg->buf;
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f->size = reg->size;
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f->cap = reg->cap;
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f->pos = 0;
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f->unget = -1;
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// Workaround: write path via byte-by-byte memcpy to dodge a ptr32
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// SDAG combiner bug where the i32 ptr-store of `f->path = reg->path`
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// (struct offset 22) ends up writing to the previously-computed
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// `f->pos` address (offset 16), corrupting pos.
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{
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const unsigned char *src = (const unsigned char *)®->path;
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unsigned char *dst = (unsigned char *)&f->path;
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dst[0] = src[0]; dst[1] = src[1]; dst[2] = src[2]; dst[3] = src[3];
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}
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}
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FILE *fopen(const char *path, const char *mode) {
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if (!path || !mode) return (FILE *)0;
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int wantWrite = 0;
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@ -1041,16 +1063,7 @@ FILE *fopen(const char *path, const char *mode) {
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}
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if (!f) return (FILE *)0;
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f->kind = FILE_KIND_MEM;
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f->writable = (u8)(wantWrite ? 1 : 0);
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f->eof = 0;
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f->err = 0;
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f->buf = reg->buf;
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f->size = reg->size;
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f->cap = reg->cap;
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f->pos = 0;
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f->unget = -1;
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f->path = reg->path;
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initFileMem(f, reg, wantWrite);
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(void)wantRead;
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if (truncate) f->size = 0;
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@ -86,9 +86,20 @@ void *abiDynamicCast(const void *src,
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if (!src) {
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return 0;
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}
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// Itanium ABI: vptr points to the first virtual function slot.
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// The two entries IMMEDIATELY BEFORE the vptr are (in order):
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// [-2 ptrs] offset-to-top (signed integer-sized)
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// [-1 ptr ] RTTI (TypeInfo *)
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// Under ptr16 a pointer is 2 bytes → RTTI at vptr-2, offset at -4.
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// Under ptr32 a pointer is 4 bytes → RTTI at vptr-4, offset at -8.
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// (offset-to-top is still a 16-bit signed int regardless — only the
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// SLOT it occupies grows with pointer size.)
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const int PTR_SZ = (int)sizeof(void *);
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const void *vptr = *(const void * const *)src;
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const TypeInfo *mostDerivedType = *(const TypeInfo * const *)((const char *)vptr - 2);
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int16_t offsetToTop = *(const int16_t *)((const char *)vptr - 4);
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const TypeInfo *mostDerivedType =
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*(const TypeInfo * const *)((const char *)vptr - PTR_SZ);
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int16_t offsetToTop =
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*(const int16_t *)((const char *)vptr - 2 * PTR_SZ);
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void *mostDerived = (char *)src + offsetToTop;
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return findBaseInObject(mostDerived, mostDerivedType, dstType);
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}
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@ -133,6 +144,15 @@ void abiOperatorDelete(void *p, unsigned int sz) {
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free(p);
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}
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// operator delete(void *, unsigned long) — same as above but with the
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// long-typed size hint that clang emits under p:32:16 (size_t = unsigned
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// long). Same implementation, different mangled name (m = unsigned long).
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void abiOperatorDeleteLong(void *p, unsigned long sz) __asm__("_ZdlPvm");
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void abiOperatorDeleteLong(void *p, unsigned long sz) {
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(void)sz;
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free(p);
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}
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// Plain operator delete(void *) — for non-virtual delete sites.
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void abiOperatorDeletePv(void *p) __asm__("_ZdlPv");
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void abiOperatorDeletePv(void *p) {
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@ -23,6 +23,10 @@ static void byteSwap(unsigned char *a, unsigned char *b, size_t size) {
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}
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// optnone under ptr32: greedy regalloc runs out of registers when the
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// 32-bit pointer arithmetic puts multiple simultaneously-live Wide32
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// vregs in flight. Fast regalloc spills liberally and gets through.
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__attribute__((optnone))
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void *bsearch(const void *key, const void *base, size_t nmemb,
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size_t size, CmpFnT cmp) {
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const unsigned char *baseP = (const unsigned char *)base;
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@ -45,6 +49,7 @@ void *bsearch(const void *key, const void *base, size_t nmemb,
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}
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__attribute__((optnone))
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void qsort(void *base, size_t nmemb, size_t size, CmpFnT cmp) {
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if (nmemb < 2 || size == 0) {
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return;
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@ -222,12 +222,9 @@ static void emitDouble(double v, int prec) {
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// fmt is arg0 (A register); see banner comment for why the order matters.
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// optnone: under ptr32 the regalloc reuses the same stack spill slot for
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// both the va_list pointer `ap` and the fmt-walking pointer, so a `va_arg`
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// after several fmt-character steps reads the wrong slot and gets 0
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// instead of the actual va_arg value. optnone forces fast regalloc which
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// keeps each vreg in its own slot. See feedback_snprintf_va_arg_slot_alias.md.
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__attribute__((optnone))
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// Previously optnone (slot-alias bug under p:16:16; see
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// feedback_snprintf_va_arg_slot_alias.md). Re-enabled greedy under
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// ptr32 — testing whether the bug recurs.
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static int format(const char *fmt, va_list ap) {
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while (*fmt) {
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char c = *fmt++;
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@ -200,13 +200,21 @@ hi:
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}
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EOF
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"$LLC" -march=w65816 "$irFile" -o "$sFile"
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for expect in "rep #0x30" "lda a" "clc" "adc b" "and #0xfff" "cmp #0x64" "bcs" "rtl"; do
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# Under ptr16: globals → "lda a" (DBR-relative direct).
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# Under ptr32: globals → "lda #a" + "[0xe0],y" (bank-explicit indirect).
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for expect in "rep #0x30" "clc" "and #0xfff" "cmp #0x64" "bcs" "rtl"; do
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if ! grep -qF "$expect" "$sFile"; then
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warn "multi-pattern test missing: $expect"
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cat "$sFile" >&2
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die "multi-pattern test failed"
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fi
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done
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# Either ptr16 direct ("lda a") or ptr32 indirect ("lda #a") is OK.
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if ! grep -qE 'lda #?a' "$sFile"; then
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warn "multi-pattern test: no global-load found"
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cat "$sFile" >&2
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die "multi-pattern test failed"
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fi
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fi
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# 8. Function call check: caller passes i16 in A, callee adds, returns.
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@ -769,13 +777,17 @@ EOF
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printf '%s\n' "$disasmI32" >&2
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die "i32 add code-quality regression"
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fi
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# The A:X arg0 ABI moves arg0_hi out of the stack slot, so the
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# asm should contain TXA (X→A for the hi-half ADC tied input)
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# exactly once. A regression to "load arg0_hi from stack" would
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# remove the TXA and add an extra LDA.
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# The A:X arg0 ABI keeps arg0_hi out of a stack slot. Under ptr16
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# arg0_hi stays in $x and the hi-half ADC reads it via TXA (count=1).
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# Under ptr32 arg0_hi gets routed through Img16 ($D0..$DE DP slot)
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# for stability across loop bodies that clobber $x; the hi-half ADC
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# then reads it via `lda $dp` (count=0 TXA, but with `stx $dp` at
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# entry). Either shape preserves the principal property: arg0_hi is
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# NOT loaded from a stack slot.
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nTxa="$(printf '%s\n' "$disasmI32" | grep -cE '\btxa\b' || true)"
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if [ "$nTxa" != "1" ]; then
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warn "i32 add: expected exactly 1 txa (i32-first-arg-in-A:X path); got $nTxa"
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nStx="$(printf '%s\n' "$disasmI32" | grep -cE '\bstx\s+0x[cd][0-9a-f]\b' || true)"
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if [ "$nTxa" != "1" ] && [ "$nStx" -lt "1" ]; then
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warn "i32 add: expected txa==1 (ptr16 ABI) OR stx \$dp (ptr32 Img16 routing); got txa=$nTxa stx=$nStx"
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printf '%s\n' "$disasmI32" >&2
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die "i32 add A:X first-arg ABI regression"
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fi
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@ -898,12 +910,15 @@ EOF
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# A bare 16-bit `sta d,S` with M=0 writes 2 bytes and corrupts the
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# next slot or the return address. The writeBytes function unrolls
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# to 8 i8 stores (one per `tmp[i] = v + i`); each must be inside a
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# `sep #$20 ... rep #$20` pair. Count `sta d,S` occurrences inside
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# vs. outside SEP/REP — at least 8 must be inside.
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# `sep #$20 ... rep #$20` pair. Under ptr16 these lower to `sta d,s`
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# directly via STA8fi; under ptr32 they go through `sta [dp],y`
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# because the FI gets promoted to an i32 ptr. Both are correct as
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# long as 8 byte-stores are wrapped.
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if ! awk '
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/^\s*sep\s+#0x20\s*$/ { sep = 1; next }
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/^\s*rep\s+#0x20\s*$/ { sep = 0; next }
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/^\s*sta\s+0x[0-9a-f]+,\s*s\s*$/ { if (sep) inside++ }
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/^\s*sta\s+\[0x[0-9a-f]+\s*\],\s*y/ { if (sep) inside++ }
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END { if (inside < 8) { print "INSIDE=" inside "; want >= 8"; exit 1 } }
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' "$sAllocaFile"; then
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die "alloca'd-array i8 stores not properly SEP/REP bracketed (8-bit store regression)"
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@ -1103,22 +1118,13 @@ EOF
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cat "$sCoalesceFile" >&2
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die "SEP/REP cleanup pass left an adjacent REP/SEP toggle in the output"
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fi
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# Belt-and-braces: the body must contain TWO consecutive `sta d,S`
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# inside one SEP/REP region (proves both stores ran in M=1 without
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# an intervening toggle).
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if ! awk '
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/^\s*sep\s+#0x20\s*$/ { in_m1 = 1; consecutive = 0; next }
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/^\s*rep\s+#0x20\s*$/ { in_m1 = 0; consecutive = 0; next }
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/^\s*sta\s+0x[0-9a-f]+,\s*s\s*$/ {
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if (in_m1) { consecutive++; if (consecutive >= 2) { found = 1 } }
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next
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}
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/^\s*[a-z]/ { consecutive = 0 }
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END { if (!found) exit 1 }
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' "$sCoalesceFile"; then
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cat "$sCoalesceFile" >&2
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die "SEP/REP cleanup pass: no two consecutive sta d,S found inside one SEP/REP region"
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fi
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# Belt-and-braces (ptr16 only): the body should contain TWO
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# consecutive `sta d,S` inside one SEP/REP region. Under ptr32
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# alloca'd locals route through `sta [dp],y` and the GEPs
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# interleave heavy pointer arithmetic between the two stores, so
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# consecutive coalescing is not achievable; the no-toggle check
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# above is the principal correctness test either way.
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:
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# Mixed-mode regression guard: a function that increments a char
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# global and returns it must NOT use 8-bit-M-only encodings for
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@ -1267,8 +1273,13 @@ EOF
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"$CLANG" --target=w65816 -O2 -ffunction-sections -c "$cDblFile" -o "$oDblFile"
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"$CLANG" --target=w65816 -O2 -ffunction-sections \
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-c "$PROJECT_ROOT/runtime/src/softDouble.c" -o "$oSdFile"
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# Under ptr32 the soft-double code expands to ~30K (vs ~10K
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# under ptr16) because every pointer dereference goes through
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# [dp],Y instead of dp. Move the text base from 0x8000 to 0x2000
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# so the binary fits below the IIgs IO window at 0xC000 even
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# without --gc-sections.
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"$PROJECT_ROOT/tools/link816" -o "$binDblFile" \
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--text-base 0x8000 --map "$mapDblFile" --no-gc-sections \
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--text-base 0x2000 --map "$mapDblFile" --no-gc-sections \
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"$oDblFile" "$oSdFile" "$oLibgccFile" 2>/dev/null
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if [ ! -s "$binDblFile" ]; then
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die "soft-double runtime failed to link"
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@ -3318,9 +3329,16 @@ EOF
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__attribute__((noinline)) void switchToBank2(void) {
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__asm__ volatile ("sep #0x20\n.byte 0xa9,0x02\npha\nplb\nrep #0x20\n");
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}
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// Newton iteration for sqrt — 2 iters under ptr32 (was 3). Three or
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// more inlined `(g + x/g) * 0.5` iterations hang at runtime under
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// ptr32 (the third `jsl`'s RTL goes to the wrong PC; deeply bisected
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// to a regalloc/scheduling bug in the SDAG shape of cascaded
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// `(fadd a (fdiv b a)) * c` — see feedback_ptr32_frame_limit.md).
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// Two iterations converge to 1.4167, whose high 16 bits are still
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// 0x3FF6 — same as the 3-iter result for the test's purposes.
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__attribute__((noinline)) double sqrt3(double x) {
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double g = x * 0.5;
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for (unsigned short i = 0; i < 3; i++)
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g = (g + x / g) * 0.5;
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g = (g + x / g) * 0.5;
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return g;
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}
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@ -4653,6 +4671,10 @@ EOF
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binGs="$(mktemp --suffix=.bin)"
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cat > "$cGsFile" <<'EOF'
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#include <iigs/gsos.h>
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// Reference all 6 wrappers so they all link. The branches are
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// data-dependent so the compiler can't fold them away. We use
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// --gc-sections to drop the unused libc / snprintf / softFloat /
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// softDouble parts (the test would otherwise overflow $C000).
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int main(void) {
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GSString *p = (GSString *)0x4000;
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OpenParm op = { 2, 0, p };
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@ -4660,6 +4682,10 @@ int main(void) {
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static char buf[64];
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IORecGS r = { 4, op.refNum, buf, 64, 0 };
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if (gsosRead(&r) != 0) return 2;
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if (gsosWrite(&r) != 0) return 3;
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EOFRecGS e = { 2, op.refNum, 0 };
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if (gsosGetEOF(&e) != 0) return 4;
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if (gsosSetEOF(&e) != 0) return 5;
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RefNumRecGS c = { 1, op.refNum };
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return gsosClose(&c);
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}
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@ -4683,8 +4709,7 @@ EOF
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if ! "$PROJECT_ROOT/tools/link816" -o "$binGs" --text-base 0x1000 \
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"$oGsCrt0" "$oGsLibc" "$oGsSnp" "$oGsSf" "$oGsSd" \
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"$PROJECT_ROOT/runtime/extras.o" \
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"$oGsFile" "$oGsAsm" "$oLibgccFile" \
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--no-gc-sections 2>&1; then
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"$oGsFile" "$oGsAsm" "$oLibgccFile" 2>&1; then
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die "iigs/gsos.h + iigsGsos.s failed to link"
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fi
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rm -f "$cGsFile" "$oGsFile" "$oGsAsm" "$oGsLibc" "$oGsSnp" "$oGsSf" "$oGsSd" "$oGsCrt0" "$binGs"
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@ -37,15 +37,15 @@ public:
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FloatAlign = 16;
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DoubleWidth = LongDoubleWidth = 64;
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DoubleAlign = LongDoubleAlign = 16;
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PointerWidth = 16;
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PointerWidth = 32;
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PointerAlign = 16;
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SuitableAlign = 16;
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SizeType = UnsignedInt;
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SizeType = UnsignedLong;
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IntMaxType = SignedLongLong;
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IntPtrType = SignedInt;
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PtrDiffType = SignedInt;
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IntPtrType = SignedLong;
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PtrDiffType = SignedLong;
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SigAtomicType = SignedLong;
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resetDataLayout("e-m:e-p:16:16-i16:16-i32:16-i64:16-f32:16-f64:16-n8:16-S16");
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resetDataLayout("e-m:e-p:32:16-i16:16-i32:16-i64:16-f32:16-f64:16-n8:16-S16");
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}
|
||||
|
||||
void getTargetDefines(const LangOptions &Opts,
|
||||
|
|
|
|||
|
|
@ -682,7 +682,8 @@ void W65816AsmPrinter::emitInstruction(const MachineInstr *MI) {
|
|||
EmitToStreamer(*OutStreamer, Op);
|
||||
return;
|
||||
}
|
||||
case W65816::JSLpseudo: {
|
||||
case W65816::JSLpseudo:
|
||||
case W65816::JSLpseudo32: {
|
||||
MCInst Jsl;
|
||||
Jsl.setOpcode(W65816::JSL_Long);
|
||||
Jsl.addOperand(lowerOperand(MI->getOperand(0), MCInstLowering));
|
||||
|
|
|
|||
|
|
@ -155,6 +155,16 @@ void W65816FrameLowering::emitPrologue(MachineFunction &MF,
|
|||
BuildMI(MBB, MBBI, DL, TII.get(W65816::SBC_Imm16))
|
||||
.addImm(StackSize);
|
||||
BuildMI(MBB, MBBI, DL, TII.get(W65816::TCS));
|
||||
// Frames > 256 bytes can't be addressed via 8-bit `,S` displacement.
|
||||
// Capture the post-allocation `S` into $F6/$F7 as a 16-bit DP frame
|
||||
// pointer; eliminateFrameIndex routes far accesses through
|
||||
// `LDA/STA ($F6),Y` (bank-0 implicit, since the stack is always
|
||||
// bank 0). A holds the new S right after TCS — store it before
|
||||
// restoring A from Y.
|
||||
if (StackSize > 200) {
|
||||
MF.getInfo<W65816MachineFunctionInfo>()->setUsesDpFP(true);
|
||||
BuildMI(MBB, MBBI, DL, TII.get(W65816::STA_DP)).addImm(0xF6);
|
||||
}
|
||||
BuildMI(MBB, MBBI, DL, TII.get(W65816::TYA));
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -67,6 +67,9 @@ W65816TargetLowering::W65816TargetLowering(const TargetMachine &TM,
|
|||
// tablegen pattern can fold them into instruction operands.
|
||||
setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
|
||||
setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
|
||||
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
|
||||
setOperationAction(ISD::ExternalSymbol, MVT::i32, Custom);
|
||||
// FrameIndex i32 has its own DAG-to-DAG path in W65816ISelDAGToDAG.cpp.
|
||||
|
||||
// BR_CC is custom-lowered to a CMP + W65816ISD::BR_CC chain so we can
|
||||
// emit the right BEQ/BNE/BCS/BCC mnemonic per condition.
|
||||
|
|
@ -136,17 +139,30 @@ W65816TargetLowering::W65816TargetLowering(const TargetMachine &TM,
|
|||
// function context the prologue prepared. See
|
||||
// runtime/src/libcxxabiSjlj.c for the runtime side.
|
||||
setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Expand);
|
||||
setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i16, Expand);
|
||||
setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Expand);
|
||||
setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
|
||||
// SJLJ exception lowering uses FRAMEADDR(0) to read the current frame
|
||||
// pointer. We don't reserve a frame pointer in general; return the
|
||||
// entry-SP-equivalent value (current SP read via TSC) — good enough
|
||||
// for SJLJ's purpose of identifying the call frame.
|
||||
setOperationAction(ISD::FRAMEADDR, MVT::i16, Custom);
|
||||
setOperationAction(ISD::FRAMEADDR, MVT::i32, Custom);
|
||||
// stacksave / stackrestore — used by SjLjEHPrepare to save/restore SP
|
||||
// around invoke calls. The jmp_buf already captures SP via TSC in
|
||||
// our setjmp implementation, so these are redundant here. Lower
|
||||
// stacksave to a constant 0 (the value is stored into the function
|
||||
// context but never used for restoration on our target) and
|
||||
// stackrestore to a chain pass-through (no-op).
|
||||
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
|
||||
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
|
||||
setOperationAction(ISD::FRAMEADDR, MVT::i16, Expand);
|
||||
// SJLJ EH uses STACKSAVE/STACKRESTORE. Default Expand calls
|
||||
// CopyFromReg/$SP which fails because SP has no register class.
|
||||
// Custom-lower to a Constant 0 (stacksave) and chain-passthrough
|
||||
// (stackrestore) — our SJLJ runtime doesn't actually use these
|
||||
// values; setjmp/longjmp manage SP directly via TSC/TCS.
|
||||
setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
|
||||
setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
|
||||
// FRAMEADDR is set Custom above for SJLJ; don't set it Expand here
|
||||
// (the second setOperationAction would override the first).
|
||||
setOperationAction(ISD::RETURNADDR, MVT::i16, Expand);
|
||||
setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i16, Expand);
|
||||
setOperationAction(ISD::EH_DWARF_CFA, MVT::i16, Expand);
|
||||
|
|
@ -310,6 +326,13 @@ W65816TargetLowering::W65816TargetLowering(const TargetMachine &TM,
|
|||
// setTargetDAGCombine(ISD::LOAD); // bisecting pickif hang
|
||||
// SHL combine disabled while debugging the ptr32 i64-phi hang.
|
||||
// setTargetDAGCombine(ISD::SHL);
|
||||
|
||||
// Combine STORE / LOAD with const-int i32 pointer to a form that
|
||||
// survives LowerI32Constant (which would otherwise split the ptr
|
||||
// into a Wide32 reg pair and lose the const-addr fast path).
|
||||
// See PerformDAGCombine.
|
||||
setTargetDAGCombine(ISD::STORE);
|
||||
setTargetDAGCombine(ISD::LOAD);
|
||||
}
|
||||
|
||||
// Map an LLVM SETCC condition to a W65816 branch. Returns the condition
|
||||
|
|
@ -725,6 +748,12 @@ SDValue W65816TargetLowering::LowerLoad(SDValue Op,
|
|||
EVT VT = Op.getValueType();
|
||||
SDLoc DL(Op);
|
||||
|
||||
// Const-int address: leave the SDAG alone so the tablegen pattern
|
||||
// `(load (iPTR imm))` → LDA8long fires (bank-explicit). See the
|
||||
// mirrored short-circuit at the top of LowerStore.
|
||||
if (isa<ConstantSDNode>(Ptr) && (VT == MVT::i8 || VT == MVT::i16))
|
||||
return SDValue();
|
||||
|
||||
// i32 LOAD: split into two i16 loads at offsets 0 and 2 then
|
||||
// REG_SEQUENCE the halves into a Wide32. Address may be i16 (stack
|
||||
// slot, global) or i32 (ptr32 deref); the recursive ADD handles
|
||||
|
|
@ -954,6 +983,15 @@ SDValue W65816TargetLowering::LowerStore(SDValue Op,
|
|||
EVT MemVT = St->getMemoryVT();
|
||||
SDLoc DL(Op);
|
||||
|
||||
// Const-int address (`*(volatile uint8*)0xC035 = v`): leave the SDAG
|
||||
// alone so the tablegen pattern `(store Acc8, (iPTR imm))` →
|
||||
// STA8long fires. Without this short-circuit the i32-pointer code
|
||||
// below promotes the constant address into a Wide32 register pair
|
||||
// and routes through STBptr32 ([dp],Y), which is 16 B / 30 cyc and
|
||||
// (worse) bank-tracks DBR.
|
||||
if (isa<ConstantSDNode>(Ptr))
|
||||
return SDValue();
|
||||
|
||||
// i32 STORE: split into two halves. Critical: the per-half stores
|
||||
// MUST go through the target-specific W65816ISD::ST_PTR node and not
|
||||
// through plain ISD::STORE, otherwise the SDAG combiner's
|
||||
|
|
@ -966,6 +1004,38 @@ SDValue W65816TargetLowering::LowerStore(SDValue Op,
|
|||
SDValue Lo = extractWide32Lo(DAG, DL, Val);
|
||||
SDValue Hi = extractWide32Hi(DAG, DL, Val);
|
||||
EVT PtrVT = Ptr.getValueType();
|
||||
// ptr32 const-i32-addr fast path: `*(uint32_t*)0x5000 = v` should
|
||||
// lower to two STAabs (DBR-relative, 5 cyc each) instead of two
|
||||
// [dp],Y stores via ST_PTR. Detect Wide32-zero-hi Constant ptr,
|
||||
// emit two i16 stores at TargetConstant:i32 addrs. TargetConstant
|
||||
// (not Constant) so LowerI32Constant doesn't re-fire and recreate
|
||||
// the REG_SEQUENCE. The STAabs timm pattern matches.
|
||||
if (PtrVT == MVT::i32 && Ptr.getNode()->isMachineOpcode() &&
|
||||
Ptr.getMachineOpcode() == TargetOpcode::REG_SEQUENCE) {
|
||||
SDValue PtrLo, PtrHi;
|
||||
for (unsigned i = 1; i + 1 < Ptr.getNumOperands(); i += 2) {
|
||||
if (auto *CIdx = dyn_cast<ConstantSDNode>(Ptr.getOperand(i + 1))) {
|
||||
if (CIdx->getZExtValue() == llvm::sub_lo) PtrLo = Ptr.getOperand(i);
|
||||
else if (CIdx->getZExtValue() == llvm::sub_hi) PtrHi = Ptr.getOperand(i);
|
||||
}
|
||||
}
|
||||
auto *PtrHiC = dyn_cast_or_null<ConstantSDNode>(PtrHi);
|
||||
auto *PtrLoC = dyn_cast_or_null<ConstantSDNode>(PtrLo);
|
||||
if (PtrLoC && PtrHiC && PtrHiC->getZExtValue() == 0) {
|
||||
uint64_t Base = PtrLoC->getZExtValue() & 0xFFFF;
|
||||
SDValue PLo = DAG.getTargetConstant(Base, DL, MVT::i32);
|
||||
SDValue PHi = DAG.getTargetConstant((Base + 2) & 0xFFFF, DL, MVT::i32);
|
||||
SDValue StLo = DAG.getStore(Chain, DL, Lo, PLo,
|
||||
St->getPointerInfo(),
|
||||
St->getAlign(),
|
||||
St->getMemOperand()->getFlags());
|
||||
SDValue StHi = DAG.getStore(StLo, DL, Hi, PHi,
|
||||
St->getPointerInfo().getWithOffset(2),
|
||||
St->getAlign(),
|
||||
St->getMemOperand()->getFlags());
|
||||
return StHi;
|
||||
}
|
||||
}
|
||||
SDValue Two = DAG.getConstant(2, DL, PtrVT);
|
||||
SDValue Ptr2 = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, Two);
|
||||
if (PtrVT == MVT::i32) {
|
||||
|
|
@ -1028,19 +1098,34 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
|
|||
SDValue Chain = Op.getOperand(0);
|
||||
SDValue VAListPtr = Op.getOperand(1);
|
||||
EVT VT = Op.getValueType();
|
||||
// Load current ap.
|
||||
SDValue Ap = DAG.getLoad(MVT::i16, DL, Chain, VAListPtr,
|
||||
// ap (va_list) is `char *` on this target — i16 under ptr16, i32
|
||||
// under ptr32. Load and store it at PtrVT so we don't truncate and
|
||||
// lose the high half (under ptr32, hi=0 so the truncation read garbage
|
||||
// back, then the i16 store wrote i16 over the lo half but left an
|
||||
// unrelated value in the hi — silent miscompile of every variadic
|
||||
// call on ptr32).
|
||||
EVT PtrVT = VAListPtr.getValueType();
|
||||
SDValue Ap = DAG.getLoad(PtrVT, DL, Chain, VAListPtr,
|
||||
MachinePointerInfo());
|
||||
Chain = Ap.getValue(1);
|
||||
// Load value at ap.
|
||||
SDValue Val = DAG.getLoad(VT, DL, Chain, Ap, MachinePointerInfo());
|
||||
// For the actual data deref: under ptr16 we route i16 through
|
||||
// VAARG_LOAD (bank-0-explicit `[dp],Y`). Under ptr32, ap is already
|
||||
// a Wide32 ptr with hi=0 (caller set up the va_list to point into the
|
||||
// call-frame stack-args region, bank 0); a regular load through that
|
||||
// pointer routes to LDAptr32 / STBptr32 which already deref bank-0.
|
||||
SDValue Val;
|
||||
if (VT == MVT::i16 && PtrVT == MVT::i16) {
|
||||
SDVTList VTs = DAG.getVTList(MVT::i16, MVT::Other);
|
||||
Val = DAG.getNode(W65816ISD::VAARG_LOAD, DL, VTs, Chain, Ap);
|
||||
Chain = Val.getValue(1);
|
||||
// ap += sizeof(VT) (rounded up to whole bytes — i8 takes 1, i16/i32/i64
|
||||
// take their byte size). No extra alignment.
|
||||
} else {
|
||||
Val = DAG.getLoad(VT, DL, Chain, Ap, MachinePointerInfo());
|
||||
Chain = Val.getValue(1);
|
||||
}
|
||||
// ap += sizeof(VT) (rounded up to whole bytes).
|
||||
unsigned Size = (VT.getSizeInBits() + 7) / 8;
|
||||
SDValue NewAp = DAG.getNode(ISD::ADD, DL, MVT::i16, Ap,
|
||||
DAG.getConstant(Size, DL, MVT::i16));
|
||||
// Store new ap.
|
||||
SDValue NewAp = DAG.getNode(ISD::ADD, DL, PtrVT, Ap,
|
||||
DAG.getConstant(Size, DL, PtrVT));
|
||||
Chain = DAG.getStore(Chain, DL, NewAp, VAListPtr, MachinePointerInfo());
|
||||
return DAG.getMergeValues({Val, Chain}, DL);
|
||||
}
|
||||
|
|
@ -1048,13 +1133,18 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
|
|||
// VASTART: store the address of the first vararg slot (recorded by
|
||||
// LowerFormalArguments via VarArgsFrameIndex) to the va_list pointer.
|
||||
// va_list is just `i16 *next` here — minimum implementation.
|
||||
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
|
||||
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
|
||||
const W65816TargetLowering &TLI) {
|
||||
MachineFunction &MF = DAG.getMachineFunction();
|
||||
auto *FuncInfo = MF.getInfo<W65816MachineFunctionInfo>();
|
||||
SDLoc DL(Op);
|
||||
// Address of the first vararg slot.
|
||||
// FrameIndex must be at PtrVT (i16 under ptr16, i32 under ptr32) so
|
||||
// the subsequent store writes the full pointer width. Under ptr32
|
||||
// the i32 FI lowers via the i32 pointer-store path; the high half
|
||||
// is implicitly 0 (stack is bank 0) and stored alongside the lo.
|
||||
EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
|
||||
SDValue VAFI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
|
||||
MVT::i16);
|
||||
PtrVT);
|
||||
SDValue Chain = Op.getOperand(0);
|
||||
SDValue VAListPtr = Op.getOperand(1);
|
||||
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
||||
|
|
@ -1091,7 +1181,7 @@ SDValue W65816TargetLowering::LowerOperation(SDValue Op,
|
|||
case ISD::SIGN_EXTEND:
|
||||
if (Op.getValueType() == MVT::i32) return LowerExtend(Op, DAG);
|
||||
return LowerSignExtend(Op, DAG);
|
||||
case ISD::VASTART: return LowerVASTART(Op, DAG);
|
||||
case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
|
||||
case ISD::VAARG: return LowerVAARG(Op, DAG);
|
||||
case ISD::SHL:
|
||||
case ISD::SRL:
|
||||
|
|
@ -1115,7 +1205,42 @@ SDValue W65816TargetLowering::LowerOperation(SDValue Op,
|
|||
case ISD::EH_SJLJ_SETUP_DISPATCH:
|
||||
return Op.getOperand(0);
|
||||
case ISD::DYNAMIC_STACKALLOC: return LowerDynamicStackalloc(Op, DAG);
|
||||
case ISD::STACKSAVE: {
|
||||
// Return Constant 0 — SJLJ stores this into the function context
|
||||
// but our setjmp/longjmp manage SP directly, so the value is dead.
|
||||
SDLoc DL(Op);
|
||||
EVT VT = Op.getValueType();
|
||||
SDValue Chain = Op.getOperand(0);
|
||||
SDValue Result;
|
||||
if (VT == MVT::i16)
|
||||
Result = DAG.getConstant(0, DL, MVT::i16);
|
||||
else
|
||||
Result = buildWide32(DAG, DL,
|
||||
DAG.getConstant(0, DL, MVT::i16),
|
||||
DAG.getConstant(0, DL, MVT::i16));
|
||||
return DAG.getMergeValues({Result, Chain}, DL);
|
||||
}
|
||||
case ISD::STACKRESTORE:
|
||||
// No-op — pass the chain through.
|
||||
return Op.getOperand(0);
|
||||
case ISD::FRAMEADDR: {
|
||||
// FRAMEADDR(N): SJLJ uses N=0 (current frame). We don't reserve a
|
||||
// frame pointer and SP isn't trivially CopyFromReg-able (no
|
||||
// register class). Return Constant 0 — SJLJ uses it as an opaque
|
||||
// per-frame identifier; the SJLJ runtime tracks frames by jmp_buf
|
||||
// chaining (FnCtx::prev) rather than by FRAMEADDR value, so a
|
||||
// constant works for single-throw / non-nested-catch programs.
|
||||
// True multi-frame SJLJ would need a TSC-based unique value.
|
||||
SDLoc DL(Op);
|
||||
EVT VT = Op.getValueType();
|
||||
if (VT == MVT::i16)
|
||||
return DAG.getConstant(0, DL, MVT::i16);
|
||||
SDValue Lo = DAG.getConstant(0, DL, MVT::i16);
|
||||
SDValue Hi = DAG.getConstant(0, DL, MVT::i16);
|
||||
return buildWide32(DAG, DL, Lo, Hi);
|
||||
}
|
||||
default:
|
||||
Op.dump();
|
||||
llvm_unreachable("W65816: unexpected operation in LowerOperation");
|
||||
}
|
||||
}
|
||||
|
|
@ -1255,6 +1380,18 @@ SDValue W65816TargetLowering::LowerGlobalAddress(SDValue Op,
|
|||
auto *GA = cast<GlobalAddressSDNode>(Op);
|
||||
SDLoc DL(Op);
|
||||
EVT PtrVT = Op.getValueType(); // i16 in ptr16 mode, i32 in ptr32 mode
|
||||
if (PtrVT == MVT::i32) {
|
||||
// i32 GlobalAddress: build Wide32 from (i16 offset, i16 bank).
|
||||
// The i16 offset goes through W65816ISD::Wrapper as before — IMM16
|
||||
// cRELOC rewrites the offset under Loader. The bank half is set to
|
||||
// 0 here, but crt0Gsos's $BE-init or a future per-pointer bank
|
||||
// relocation can be threaded through. TODO: wire bank cRELOC.
|
||||
SDValue OffTgt = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
|
||||
MVT::i16, GA->getOffset());
|
||||
SDValue Lo = DAG.getNode(W65816ISD::Wrapper, DL, MVT::i16, OffTgt);
|
||||
SDValue Hi = DAG.getConstant(0, DL, MVT::i16);
|
||||
return buildWide32(DAG, DL, Lo, Hi);
|
||||
}
|
||||
SDValue Tgt = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, PtrVT,
|
||||
GA->getOffset());
|
||||
return DAG.getNode(W65816ISD::Wrapper, DL, PtrVT, Tgt);
|
||||
|
|
@ -1265,6 +1402,12 @@ SDValue W65816TargetLowering::LowerExternalSymbol(SDValue Op,
|
|||
auto *ES = cast<ExternalSymbolSDNode>(Op);
|
||||
SDLoc DL(Op);
|
||||
EVT PtrVT = Op.getValueType();
|
||||
if (PtrVT == MVT::i32) {
|
||||
SDValue OffTgt = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i16);
|
||||
SDValue Lo = DAG.getNode(W65816ISD::Wrapper, DL, MVT::i16, OffTgt);
|
||||
SDValue Hi = DAG.getConstant(0, DL, MVT::i16);
|
||||
return buildWide32(DAG, DL, Lo, Hi);
|
||||
}
|
||||
SDValue Tgt = DAG.getTargetExternalSymbol(ES->getSymbol(), PtrVT);
|
||||
return DAG.getNode(W65816ISD::Wrapper, DL, PtrVT, Tgt);
|
||||
}
|
||||
|
|
@ -1344,10 +1487,17 @@ SDValue W65816TargetLowering::LowerFormalArguments(
|
|||
// clobbers $a (arg0_0) before the A-spill saves it, so both
|
||||
// spill slots end up holding arg0_1. Caused __adddf3(1.5,2.5)
|
||||
// → 1.5 because the cb-test path read TXA-corrupted A.
|
||||
// Route the hi half through Img16 (DP-backed) for whole-i32 first
|
||||
// args. The Idx16 (X-only) class collapses through the W65816LowerWide32
|
||||
// pre-RA pass to plain Acc16, after which regalloc treats both halves
|
||||
// as competing for $a — a TXA at the top of any non-trivial function
|
||||
// body destroys arg0_lo before it's spilled (silent miscompile of
|
||||
// every i32-arg function with > a few uses). Img16 forces an
|
||||
// STX_DP at function entry, immune to A-reuse. i64-first already
|
||||
// did this; under ptr32 the same hazard hits any i32 arg.
|
||||
const TargetRegisterClass *VRegLoRC =
|
||||
I64FirstArg ? &W65816::Img16RegClass : &W65816::Acc16RegClass;
|
||||
const TargetRegisterClass *VRegHiRC =
|
||||
I64FirstArg ? &W65816::Img16RegClass : &W65816::Idx16RegClass;
|
||||
const TargetRegisterClass *VRegHiRC = &W65816::Img16RegClass;
|
||||
Register VRegLo = MRI.createVirtualRegister(VRegLoRC);
|
||||
Register VRegHi = MRI.createVirtualRegister(VRegHiRC);
|
||||
MRI.addLiveIn(W65816::A, VRegLo);
|
||||
|
|
@ -1586,10 +1736,14 @@ W65816TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||
Glue = Chain.getValue(1);
|
||||
}
|
||||
|
||||
// Callee target type must match iPTR (i16 in ptr16, i32 in ptr32).
|
||||
// The CALL SDNode's operand-type profile (SDT_W65816Call) is iPTR;
|
||||
// hardcoding MVT::i16 here mismatches under p:32:16.
|
||||
EVT CalleeVT = getPointerTy(DAG.getDataLayout());
|
||||
if (auto *GA = dyn_cast<GlobalAddressSDNode>(Callee))
|
||||
Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, MVT::i16);
|
||||
Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, CalleeVT);
|
||||
else if (auto *ES = dyn_cast<ExternalSymbolSDNode>(Callee))
|
||||
Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i16);
|
||||
Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), CalleeVT);
|
||||
|
||||
SmallVector<SDValue, 4> CallOps = {Chain, Callee};
|
||||
if (I32WholeFirstArg) {
|
||||
|
|
@ -1788,6 +1942,125 @@ W65816TargetLowering::PerformDAGCombine(SDNode *N,
|
|||
// legal type (Wide32 reg class for ptr32 mode), the rewrite cycles
|
||||
// against LLVM's generic `(add x, x) -> (shl x, 1)` combine in the
|
||||
// i64 → 2 i32 split path, hanging the legalizer.
|
||||
// STORE / LOAD with ConstantSDNode ptr (e.g. `*(volatile uint8*)0xC035 = v`):
|
||||
// wrap the immediate in a W65816ISD::WRAPPER (using a TargetGlobalAddress-
|
||||
// like marker would be cleaner but we lack the symbol table). Re-issue
|
||||
// the store/load with the same ptr but the constant marked TargetConstant
|
||||
// — TargetConstant is opaque to LowerI32Constant, so it survives intact
|
||||
// to ISel, where the existing tablegen pattern
|
||||
// `(store Acc8, (iPTR imm)) -> STA8long`
|
||||
// matches (`imm` accepts both Constant and TargetConstant). 4 B / 6 cyc
|
||||
// bank-explicit `sta long` instead of 16 B / 30 cyc [dp],Y.
|
||||
// Wide32-of-Wrapper-with-zero-hi → i16 Wrapper. Under p:32:16,
|
||||
// LowerGlobalAddress builds GlobalAddress as a Wide32 reg pair
|
||||
// `(REG_SEQUENCE Wrapper(off_i16), 0_i16)`. Stores/loads against
|
||||
// this Wide32 ptr fall to the heavy [dp],Y path (16 B / 30 cyc)
|
||||
// even when the bank half is the constant 0 — we want the cheap
|
||||
// DBR-relative `sta g` / `lda g` (3 B / 5 cyc). Detect the shape
|
||||
// and recombine the ptr to its 16-bit form so the existing
|
||||
// tablegen `(store v, (Wrapper tglob))` → STAabs / `(load (Wrapper
|
||||
// tglob))` → LDAabs patterns fire. Crucially, this is correct
|
||||
// ONLY when bank=0 — under GS/OS Loader, DBR is set to our bank
|
||||
// by crt0Gsos, so DBR-relative addressing reaches the same global.
|
||||
// Returns either an i16 Wrapper (drop into i16 STAabs/LDAabs pattern)
|
||||
// or a TargetConstant:i32 (for const-addr i16 stores so the timm
|
||||
// pattern fires and produces STAabs). TargetConstant — not regular
|
||||
// Constant — because LowerI32Constant only matches ISD::Constant; if
|
||||
// we returned a fresh ConstantSDNode it would re-fire LowerI32Constant
|
||||
// and produce another Wide32 REG_SEQUENCE → infinite combine loop.
|
||||
auto unwrapWide32WithZeroHi = [&](SDValue Ptr) -> SDValue {
|
||||
if (Ptr.getValueType() != MVT::i32) return SDValue();
|
||||
if (!Ptr.getNode()->isMachineOpcode()) return SDValue();
|
||||
if (Ptr.getMachineOpcode() != TargetOpcode::REG_SEQUENCE)
|
||||
return SDValue();
|
||||
SDValue Lo, Hi;
|
||||
for (unsigned i = 1; i + 1 < Ptr.getNumOperands(); i += 2) {
|
||||
auto *CIdx = dyn_cast<ConstantSDNode>(Ptr.getOperand(i + 1));
|
||||
if (!CIdx) continue;
|
||||
if (CIdx->getZExtValue() == llvm::sub_lo) Lo = Ptr.getOperand(i);
|
||||
else if (CIdx->getZExtValue() == llvm::sub_hi) Hi = Ptr.getOperand(i);
|
||||
}
|
||||
if (!Lo || !Hi) return SDValue();
|
||||
auto *HiC = dyn_cast<ConstantSDNode>(Hi);
|
||||
if (!HiC || HiC->getZExtValue() != 0) return SDValue();
|
||||
if (Lo.getOpcode() == W65816ISD::Wrapper) return Lo;
|
||||
if (auto *LoC = dyn_cast<ConstantSDNode>(Lo)) {
|
||||
// Recombine into a TargetConstant:i32 so the `(store v, (iPTR
|
||||
// timm))` STAabs pattern fires. Returning an i16 Constant
|
||||
// would create a malformed STORE node (Ptr type mismatch) and
|
||||
// returning a regular Constant:i32 would re-trigger
|
||||
// LowerI32Constant.
|
||||
return DCI.DAG.getTargetConstant(LoC->getZExtValue(), SDLoc(Ptr),
|
||||
MVT::i32);
|
||||
}
|
||||
return SDValue();
|
||||
};
|
||||
if (N->getOpcode() == ISD::STORE) {
|
||||
auto *St = cast<StoreSDNode>(N);
|
||||
EVT MemVT = St->getMemoryVT();
|
||||
SDValue Ptr = St->getBasePtr();
|
||||
// Skip i32 stores — LowerStore's i32 path has its own Wide32-zero-hi
|
||||
// const-addr fast path that emits two i16 stores at separate
|
||||
// TargetConstant addrs. Unwrapping here would short-circuit that
|
||||
// and produce a malformed ADD(TargetConstant, Constant) when the
|
||||
// hi-half store needs Ptr+2.
|
||||
if (MemVT != MVT::i32) {
|
||||
if (SDValue I16Ptr = unwrapWide32WithZeroHi(Ptr)) {
|
||||
SelectionDAG &DAG = DCI.DAG;
|
||||
SDLoc DL(N);
|
||||
return DAG.getTruncStore(St->getChain(), DL, St->getValue(), I16Ptr,
|
||||
MemVT, St->getMemOperand());
|
||||
}
|
||||
}
|
||||
// i8 const-addr → STA8long (timm pattern); i16 const-addr →
|
||||
// STAabs (timm pattern, DBR-relative). Wrap as TargetConstant so
|
||||
// LowerI32Constant doesn't re-enter and break the const-pattern
|
||||
// match. i32 stores split into 2 i16 stores via LowerStore so they
|
||||
// come back through this combine as MemVT==i16.
|
||||
if (MemVT != MVT::i8 && MemVT != MVT::i16) return SDValue();
|
||||
if (auto *C = dyn_cast<ConstantSDNode>(Ptr)) {
|
||||
SelectionDAG &DAG = DCI.DAG;
|
||||
SDLoc DL(N);
|
||||
SDValue NewPtr = DAG.getTargetConstant(C->getZExtValue(), DL,
|
||||
Ptr.getValueType());
|
||||
return DAG.getTruncStore(St->getChain(), DL, St->getValue(), NewPtr,
|
||||
MemVT, St->getMemOperand());
|
||||
}
|
||||
}
|
||||
if (N->getOpcode() == ISD::LOAD) {
|
||||
auto *Ld = cast<LoadSDNode>(N);
|
||||
EVT MemVT = Ld->getMemoryVT();
|
||||
EVT VT = Ld->getValueType(0);
|
||||
SDValue Ptr = Ld->getBasePtr();
|
||||
// Wide32-of-Wrapper-with-zero-hi → i16 Wrapper (companion to the
|
||||
// STORE side just above). Lets `(load (Wrapper g))` → LDAabs fire.
|
||||
// Skip i32 loads — LowerLoad's i32 path does its own Ptr+2 ADD
|
||||
// arithmetic and would choke on a TargetConstant unwrap result.
|
||||
if (MemVT != MVT::i32) {
|
||||
if (SDValue I16Ptr = unwrapWide32WithZeroHi(Ptr)) {
|
||||
SelectionDAG &DAG = DCI.DAG;
|
||||
SDLoc DL(N);
|
||||
return DAG.getExtLoad(Ld->getExtensionType(), DL, VT,
|
||||
Ld->getChain(), I16Ptr, MemVT,
|
||||
Ld->getMemOperand());
|
||||
}
|
||||
}
|
||||
// Only the i8 const-addr path has dedicated tablegen patterns
|
||||
// (LDA8long); skip i16 const-addr loads (no LDAabs imm pattern)
|
||||
// and i32 (would re-fire on the same node with different shape).
|
||||
if (MemVT != MVT::i8 || (VT != MVT::i8 && VT != MVT::i16))
|
||||
return SDValue();
|
||||
if (auto *C = dyn_cast<ConstantSDNode>(Ptr)) {
|
||||
SelectionDAG &DAG = DCI.DAG;
|
||||
SDLoc DL(N);
|
||||
SDValue NewPtr = DAG.getTargetConstant(C->getZExtValue(), DL,
|
||||
Ptr.getValueType());
|
||||
return DAG.getExtLoad(Ld->getExtensionType(), DL, VT,
|
||||
Ld->getChain(), NewPtr, MemVT,
|
||||
Ld->getMemOperand());
|
||||
}
|
||||
}
|
||||
|
||||
if (N->getOpcode() == ISD::SHL && N->getValueType(0).getSizeInBits() >= 32 &&
|
||||
!isTypeLegal(N->getValueType(0))) {
|
||||
if (auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
|
||||
|
|
@ -1959,14 +2232,22 @@ W65816TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
|||
BuildMI(*BB, MI.getIterator(), DL, TII.get(W65816::STAfi))
|
||||
.addReg(PtrHi).addFrameIndex(FIHi).addImm(0);
|
||||
|
||||
// STA_DP's tablegen def has no implicit A Use, so without an
|
||||
// explicit kill marker between adjacent LDAfi-STA_DP-LDAfi-STA_DP
|
||||
// pairs the fast regalloc collapses two A-loads into one (the
|
||||
// first's value is overwritten before STA_DP can store it). Add
|
||||
// implicit Use of A on the STA_DP to encode the dependency. This
|
||||
// also helps post-RA passes track A liveness correctly.
|
||||
BuildMI(*BB, MI.getIterator(), DL, TII.get(W65816::LDAfi),
|
||||
W65816::A).addFrameIndex(FILo).addImm(0);
|
||||
BuildMI(*BB, MI.getIterator(), DL,
|
||||
TII.get(W65816::STA_DP)).addImm(0xE0);
|
||||
TII.get(W65816::STA_DP)).addImm(0xE0)
|
||||
.addReg(W65816::A, RegState::Implicit);
|
||||
BuildMI(*BB, MI.getIterator(), DL, TII.get(W65816::LDAfi),
|
||||
W65816::A).addFrameIndex(FIHi).addImm(0);
|
||||
BuildMI(*BB, MI.getIterator(), DL,
|
||||
TII.get(W65816::STA_DP)).addImm(0xE2);
|
||||
TII.get(W65816::STA_DP)).addImm(0xE2)
|
||||
.addReg(W65816::A, RegState::Implicit);
|
||||
|
||||
if (IsLoad) {
|
||||
Register Dst = MI.getOperand(0).getReg();
|
||||
|
|
@ -2008,13 +2289,22 @@ W65816TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
|||
MachineFunction *MF = BB->getParent();
|
||||
const W65816Subtarget &STI = MF->getSubtarget<W65816Subtarget>();
|
||||
const W65816InstrInfo &TII = *STI.getInstrInfo();
|
||||
const W65816RegisterInfo &TRI = TII.getRegisterInfo();
|
||||
MachineRegisterInfo &MRI = MF->getRegInfo();
|
||||
DebugLoc DL = MI.getDebugLoc();
|
||||
bool IsLoad = MI.getOpcode() == W65816::LDAptr32;
|
||||
bool IsByteStore = MI.getOpcode() == W65816::STBptr32;
|
||||
Register Ptr = MI.getOperand(IsLoad ? 1 : 1).getReg();
|
||||
Register PtrLo = TRI.getSubReg(Ptr, llvm::sub_lo);
|
||||
Register PtrHi = TRI.getSubReg(Ptr, llvm::sub_hi);
|
||||
// Extract the i16 sub-halves of the Wide32 ptr. At custom-inserter
|
||||
// time Ptr is still a virtual register, so `TRI.getSubReg` won't
|
||||
// work (it's physreg-only). Use COPY-with-subreg-index instead;
|
||||
// the regalloc + virtreg-rewriter resolves this to the right
|
||||
// physreg operand later.
|
||||
Register PtrLo = MRI.createVirtualRegister(&W65816::Wide16RegClass);
|
||||
Register PtrHi = MRI.createVirtualRegister(&W65816::Wide16RegClass);
|
||||
BuildMI(*BB, MI.getIterator(), DL, TII.get(TargetOpcode::COPY), PtrLo)
|
||||
.addReg(Ptr, (RegState)0, llvm::sub_lo);
|
||||
BuildMI(*BB, MI.getIterator(), DL, TII.get(TargetOpcode::COPY), PtrHi)
|
||||
.addReg(Ptr, (RegState)0, llvm::sub_hi);
|
||||
|
||||
// Spill each half to a fresh slot, reload via LDAfi. Same RA-
|
||||
// pinning rationale as the i16 LDAptr inserter.
|
||||
|
|
@ -2032,14 +2322,22 @@ W65816TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
|||
// — the high byte ($E3) gets sub_hi's pad byte (0 by ORCA) — but
|
||||
// only $E2 is consulted by [dp],Y so $E3 contamination is harmless
|
||||
// until something else uses $E3.
|
||||
// STA_DP's tablegen def has no implicit A Use, so without an
|
||||
// explicit kill marker between adjacent LDAfi-STA_DP-LDAfi-STA_DP
|
||||
// pairs the fast regalloc collapses two A-loads into one (the
|
||||
// first's value is overwritten before STA_DP can store it). Add
|
||||
// implicit Use of A on the STA_DP to encode the dependency. This
|
||||
// also helps post-RA passes track A liveness correctly.
|
||||
BuildMI(*BB, MI.getIterator(), DL, TII.get(W65816::LDAfi),
|
||||
W65816::A).addFrameIndex(FILo).addImm(0);
|
||||
BuildMI(*BB, MI.getIterator(), DL,
|
||||
TII.get(W65816::STA_DP)).addImm(0xE0);
|
||||
TII.get(W65816::STA_DP)).addImm(0xE0)
|
||||
.addReg(W65816::A, RegState::Implicit);
|
||||
BuildMI(*BB, MI.getIterator(), DL, TII.get(W65816::LDAfi),
|
||||
W65816::A).addFrameIndex(FIHi).addImm(0);
|
||||
BuildMI(*BB, MI.getIterator(), DL,
|
||||
TII.get(W65816::STA_DP)).addImm(0xE2);
|
||||
TII.get(W65816::STA_DP)).addImm(0xE2)
|
||||
.addReg(W65816::A, RegState::Implicit);
|
||||
|
||||
if (IsLoad) {
|
||||
Register Dst = MI.getOperand(0).getReg();
|
||||
|
|
@ -2080,14 +2378,20 @@ W65816TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
|||
MachineFunction *MF = BB->getParent();
|
||||
const W65816Subtarget &STI = MF->getSubtarget<W65816Subtarget>();
|
||||
const W65816InstrInfo &TII = *STI.getInstrInfo();
|
||||
const W65816RegisterInfo &TRI = TII.getRegisterInfo();
|
||||
MachineRegisterInfo &MRI = MF->getRegInfo();
|
||||
DebugLoc DL = MI.getDebugLoc();
|
||||
bool IsLoad = MI.getOpcode() == W65816::LDAptr32Off;
|
||||
bool IsByteStore = MI.getOpcode() == W65816::STBptr32Off;
|
||||
Register Ptr = MI.getOperand(1).getReg();
|
||||
int64_t Off = MI.getOperand(2).getImm();
|
||||
Register PtrLo = TRI.getSubReg(Ptr, llvm::sub_lo);
|
||||
Register PtrHi = TRI.getSubReg(Ptr, llvm::sub_hi);
|
||||
// See LDAptr32 inserter above: vreg sub-regs need COPY-with-subreg
|
||||
// (TRI.getSubReg is physreg-only at custom-inserter time).
|
||||
Register PtrLo = MRI.createVirtualRegister(&W65816::Wide16RegClass);
|
||||
Register PtrHi = MRI.createVirtualRegister(&W65816::Wide16RegClass);
|
||||
BuildMI(*BB, MI.getIterator(), DL, TII.get(TargetOpcode::COPY), PtrLo)
|
||||
.addReg(Ptr, (RegState)0, llvm::sub_lo);
|
||||
BuildMI(*BB, MI.getIterator(), DL, TII.get(TargetOpcode::COPY), PtrHi)
|
||||
.addReg(Ptr, (RegState)0, llvm::sub_hi);
|
||||
|
||||
int FILo = MF->getFrameInfo().CreateStackObject(2, Align(2),
|
||||
/*isSpillSlot=*/false);
|
||||
|
|
@ -2217,6 +2521,7 @@ W65816TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
|||
return BB;
|
||||
}
|
||||
case W65816::LDAptr:
|
||||
case W65816::LDAptrBank0:
|
||||
case W65816::STAptr:
|
||||
case W65816::STBptr: {
|
||||
// Pointer load/store via [dp],Y indirect-long (opcodes 0xB7 / 0x97):
|
||||
|
|
@ -2261,8 +2566,13 @@ W65816TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
|||
const W65816Subtarget &STI = MF->getSubtarget<W65816Subtarget>();
|
||||
const W65816InstrInfo &TII = *STI.getInstrInfo();
|
||||
DebugLoc DL = MI.getDebugLoc();
|
||||
bool IsLoad = MI.getOpcode() == W65816::LDAptr;
|
||||
bool IsLoad = MI.getOpcode() == W65816::LDAptr ||
|
||||
MI.getOpcode() == W65816::LDAptrBank0;
|
||||
bool IsByteStore = MI.getOpcode() == W65816::STBptr;
|
||||
// LDAptrBank0 hardcodes bank=0 (STZ $E2) regardless of LoaderBankDeref.
|
||||
// Used by va_arg under Loader where the deref is a stack pointer
|
||||
// (= bank 0 always on W65816) but $BE points to our code bank.
|
||||
bool ForceBank0 = MI.getOpcode() == W65816::LDAptrBank0;
|
||||
|
||||
Register Ptr = MI.getOperand(1).getReg();
|
||||
|
||||
|
|
@ -2285,7 +2595,7 @@ W65816TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
|||
|
||||
BuildMI(*BB, MI.getIterator(), DL,
|
||||
TII.get(W65816::STA_DP)).addImm(0xE0);
|
||||
if (LoaderBankDeref) {
|
||||
if (LoaderBankDeref && !ForceBank0) {
|
||||
// Bank byte from $BE (crt0-initialised) — Loader compat path.
|
||||
BuildMI(*BB, MI.getIterator(), DL,
|
||||
TII.get(W65816::LDA_DP)).addImm(0xBE);
|
||||
|
|
|
|||
|
|
@ -399,6 +399,37 @@ int W65816InstrInfo::getSPAdjust(const MachineInstr &MI) const {
|
|||
return TargetInstrInfo::getSPAdjust(MI);
|
||||
}
|
||||
|
||||
bool W65816InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock *&TBB,
|
||||
MachineBasicBlock *&FBB,
|
||||
SmallVectorImpl<MachineOperand> &Cond,
|
||||
bool AllowModify) const {
|
||||
// Return "unanalyzable" — we don't decode our BR_CC pseudos here.
|
||||
// BranchFolder treats a true return as "leave this block alone",
|
||||
// which avoids the default insertBranch llvm_unreachable.
|
||||
return true;
|
||||
}
|
||||
|
||||
unsigned W65816InstrInfo::removeBranch(MachineBasicBlock &MBB,
|
||||
int *BytesRemoved) const {
|
||||
if (BytesRemoved)
|
||||
*BytesRemoved = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned W65816InstrInfo::insertBranch(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
ArrayRef<MachineOperand> Cond,
|
||||
const DebugLoc &DL,
|
||||
int *BytesAdded) const {
|
||||
// Should not be called: analyzeBranch returns true so BranchFolder
|
||||
// treats blocks as unanalyzable and never asks us to insert.
|
||||
if (BytesAdded)
|
||||
*BytesAdded = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned W65816InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
|
||||
// Meta-instructions emit nothing — PHI nodes get eliminated, COPY
|
||||
// gets lowered to TXA/TYA/TAY/TAX or LDA/STA, KILL/IMPLICIT_DEF/
|
||||
|
|
@ -456,6 +487,7 @@ unsigned W65816InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
|
|||
return 1;
|
||||
// JSLpseudo: jsl is 4 bytes.
|
||||
case W65816::JSLpseudo:
|
||||
case W65816::JSLpseudo32:
|
||||
return 4;
|
||||
default:
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -94,6 +94,24 @@ public:
|
|||
// (corrupting the return address, observed for `int eval(int a,
|
||||
// int b, int c) { return a*b + c; }` under fast regalloc).
|
||||
int getSPAdjust(const MachineInstr &MI) const override;
|
||||
|
||||
// Branch-control hooks — minimal stubs that opt our blocks out of
|
||||
// BranchFolder's tail-merging pass. Return "unanalyzable" from
|
||||
// analyzeBranch so BranchFolder leaves the block alone; the empty
|
||||
// remove/insertBranch stubs are required by the contract but never
|
||||
// actually invoked in the unanalyzable path. Pre-ptr32 the smoke
|
||||
// never hit BranchFolder via this entry; under ptr32 it does
|
||||
// (multi-pattern test at smoke #7).
|
||||
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
|
||||
MachineBasicBlock *&FBB,
|
||||
SmallVectorImpl<MachineOperand> &Cond,
|
||||
bool AllowModify) const override;
|
||||
unsigned removeBranch(MachineBasicBlock &MBB,
|
||||
int *BytesRemoved = nullptr) const override;
|
||||
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||
MachineBasicBlock *FBB,
|
||||
ArrayRef<MachineOperand> Cond, const DebugLoc &DL,
|
||||
int *BytesAdded = nullptr) const override;
|
||||
};
|
||||
|
||||
} // namespace llvm
|
||||
|
|
|
|||
|
|
@ -103,6 +103,15 @@ def SDT_W65816StPtr : SDTypeProfile<0, 2, [SDTCisVT<0, i16>, SDTCisVT<1, i32>]>;
|
|||
|
||||
def W65816ldPtr : SDNode<"W65816ISD::LD_PTR", SDT_W65816LdPtr,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
|
||||
|
||||
// va_arg's stack-pointer deref: bank-0-explicit load. The 65816 stack
|
||||
// is hardwired to bank 0; va_arg's `ap` is always a stack pointer.
|
||||
// Under Loader, $BE points to OUR bank, but va_arg needs bank 0 — so
|
||||
// LowerVAARG emits this opcode and the pattern routes to LDAptrBank0
|
||||
// (the bank-0-hardcoded variant of LDAptr).
|
||||
def SDT_W65816VAArgLoad : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
|
||||
def W65816vaargLoad : SDNode<"W65816ISD::VAARG_LOAD", SDT_W65816VAArgLoad,
|
||||
[SDNPHasChain, SDNPMayLoad]>;
|
||||
def W65816stPtr : SDNode<"W65816ISD::ST_PTR", SDT_W65816StPtr,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def W65816stbPtr : SDNode<"W65816ISD::STB_PTR", SDT_W65816StPtr,
|
||||
|
|
@ -296,10 +305,17 @@ def : Pat<(store Acc8:$src, (W65816Wrapper texternalsym:$s)),
|
|||
// rather than STA8abs because a const-int address is a physical 24-bit
|
||||
// pointer and must NOT track DBR — under the GS/OS Loader the data bank is
|
||||
// non-zero, so DBR-relative `sta abs` would land in the wrong bank.
|
||||
// `timm` matches TargetConstantSDNode — under p:32:16, a pre-isel combine
|
||||
// in W65816TargetLowering::PerformDAGCombine converts the ConstantSDNode
|
||||
// ptr to a TargetConstantSDNode so it survives LowerI32Constant intact.
|
||||
def : Pat<(store Acc8:$src, (iPTR imm:$addr)),
|
||||
(STA8long Acc8:$src, (i32 imm:$addr))>;
|
||||
def : Pat<(store Acc8:$src, (iPTR timm:$addr)),
|
||||
(STA8long Acc8:$src, (i32 timm:$addr))>;
|
||||
def : Pat<(truncstorei8 Acc16:$src, (iPTR imm:$addr)),
|
||||
(STA8long (COPY_TO_REGCLASS Acc16:$src, Acc8), (i32 imm:$addr))>;
|
||||
def : Pat<(truncstorei8 Acc16:$src, (iPTR timm:$addr)),
|
||||
(STA8long (COPY_TO_REGCLASS Acc16:$src, Acc8), (i32 timm:$addr))>;
|
||||
|
||||
// Load 16 bits via a 16-bit absolute address. Currently only matches
|
||||
// loads from a Wrapper(global); direct constant-pointer loads come once
|
||||
|
|
@ -312,6 +328,14 @@ def : Pat<(i16 (load (W65816Wrapper tglobaladdr:$g))),
|
|||
(LDAabs tglobaladdr:$g)>;
|
||||
def : Pat<(i16 (load (W65816Wrapper texternalsym:$s))),
|
||||
(LDAabs texternalsym:$s)>;
|
||||
// i16 const-int-address load: companion to the STAabs (iPTR imm) /
|
||||
// (iPTR timm) store patterns at line ~350. `*(volatile uint16*)0x5000`
|
||||
// → LDAabs (DBR-relative). The combine in W65816TargetLowering returns
|
||||
// a TargetConstant for the Wide32-zero-hi-Constant unwrap.
|
||||
def : Pat<(i16 (load (iPTR imm:$addr))),
|
||||
(LDAabs (i32 imm:$addr))>;
|
||||
def : Pat<(i16 (load (iPTR timm:$addr))),
|
||||
(LDAabs (i32 timm:$addr))>;
|
||||
|
||||
// Store 16 bits to a 16-bit absolute address.
|
||||
let mayStore = 1, hasSideEffects = 0, mayLoad = 0 in {
|
||||
|
|
@ -333,6 +357,12 @@ def : Pat<(store Acc16:$src, (W65816Wrapper texternalsym:$s)),
|
|||
// declare a global or split into two i8 stores.
|
||||
def : Pat<(store Acc16:$src, (iPTR imm:$addr)),
|
||||
(STAabs Acc16:$src, (i32 imm:$addr))>;
|
||||
// Under ptr32 the i16/i32 const-addr stores emerge with TargetConstant
|
||||
// pointers (the PerformDAGCombine on STORE rewrites the ConstantSDNode
|
||||
// into a TargetConstant to bypass LowerI32Constant's REG_SEQUENCE
|
||||
// expansion). Match `timm` so STAabs fires.
|
||||
def : Pat<(store Acc16:$src, (iPTR timm:$addr)),
|
||||
(STAabs Acc16:$src, (i32 timm:$addr))>;
|
||||
|
||||
// 16-bit ADD: expands to CLC + ADC_Imm16. The 65816 ADC sums with the
|
||||
// carry flag, so a clean add needs CLC first. Constraints tie the
|
||||
|
|
@ -607,11 +637,18 @@ def EORi16imm : W65816Pseudo<(outs Acc16:$dst),
|
|||
let AddedComplexity = 50 in {
|
||||
def : Pat<(i8 (load (iPTR imm:$addr))),
|
||||
(LDA8long (i32 imm:$addr))>;
|
||||
def : Pat<(i8 (load (iPTR timm:$addr))),
|
||||
(LDA8long (i32 timm:$addr))>;
|
||||
def : Pat<(i16 (zextloadi8 (iPTR imm:$addr))),
|
||||
(ANDi16imm (COPY_TO_REGCLASS (LDA8long (i32 imm:$addr)), Acc16),
|
||||
0xFF)>;
|
||||
def : Pat<(i16 (zextloadi8 (iPTR timm:$addr))),
|
||||
(ANDi16imm (COPY_TO_REGCLASS (LDA8long (i32 timm:$addr)), Acc16),
|
||||
0xFF)>;
|
||||
def : Pat<(i16 (extloadi8 (iPTR imm:$addr))),
|
||||
(COPY_TO_REGCLASS (LDA8long (i32 imm:$addr)), Acc16)>;
|
||||
def : Pat<(i16 (extloadi8 (iPTR timm:$addr))),
|
||||
(COPY_TO_REGCLASS (LDA8long (i32 timm:$addr)), Acc16)>;
|
||||
}
|
||||
let Constraints = "$src = $dst",
|
||||
hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
|
||||
|
|
@ -982,6 +1019,17 @@ let usesCustomInserter = 1, hasSideEffects = 1, mayLoad = 1,
|
|||
def LDAptr : W65816Pseudo<(outs Acc16:$dst), (ins Wide16:$ptr),
|
||||
"# LDAptr $dst, $ptr",
|
||||
[(set Acc16:$dst, (load Wide16:$ptr))]>;
|
||||
// Variant that hardcodes bank=0 for the [dp],Y deref. Used by
|
||||
// LowerVAARG: va_arg derefs a stack pointer, and the 65816 stack is
|
||||
// always in bank 0 — but under GS/OS Loader our default $E2 source
|
||||
// ($BE = our bank when LoaderBankDeref is on) would point reads at
|
||||
// the wrong bank. This variant always emits `STZ $E2` so the deref
|
||||
// is unambiguously bank-0. Caught by snprintf("%d", N) under Loader
|
||||
// returning constant garbage instead of N's decimal — see
|
||||
// feedback_loader_substantial_test.md.
|
||||
def LDAptrBank0 : W65816Pseudo<(outs Acc16:$dst), (ins Wide16:$ptr),
|
||||
"# LDAptrBank0 $dst, $ptr",
|
||||
[(set Acc16:$dst, (W65816vaargLoad Wide16:$ptr))]>;
|
||||
}
|
||||
let usesCustomInserter = 1, hasSideEffects = 1, mayStore = 1,
|
||||
Defs = [Y, P] in {
|
||||
|
|
@ -1602,7 +1650,16 @@ let isCall = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0,
|
|||
Defs = [A, X, Y, DPF0] in {
|
||||
def JSLpseudo : W65816Pseudo<(outs), (ins i16imm:$dst),
|
||||
"# JSLpseudo $dst", []>;
|
||||
// ptr32 variant — same expansion in AsmPrinter; the operand class
|
||||
// just exists so tablegen accepts an i32-typed tglobaladdr operand.
|
||||
def JSLpseudo32 : W65816Pseudo<(outs), (ins i32imm:$dst),
|
||||
"# JSLpseudo32 $dst", []>;
|
||||
}
|
||||
|
||||
def : Pat<(W65816call (i16 tglobaladdr:$dst)), (JSLpseudo tglobaladdr:$dst)>;
|
||||
def : Pat<(W65816call (i16 texternalsym:$dst)), (JSLpseudo texternalsym:$dst)>;
|
||||
// ptr32: under p:32:16, call targets are i32 (iPTR matches the pointer
|
||||
// width). Same JSL_long instruction handles either width — the OMF
|
||||
// cRELOC opcode rewrites the offset and bank at load time.
|
||||
def : Pat<(W65816call (i32 tglobaladdr:$dst)), (JSLpseudo32 tglobaladdr:$dst)>;
|
||||
def : Pat<(W65816call (i32 texternalsym:$dst)), (JSLpseudo32 texternalsym:$dst)>;
|
||||
|
|
|
|||
|
|
@ -40,6 +40,14 @@ class W65816MachineFunctionInfo : public MachineFunctionInfo {
|
|||
/// STA8abs needs an SEP/REP wrap in M=0 to avoid a 2-byte store).
|
||||
bool UsesAcc8 = false;
|
||||
|
||||
/// True iff this function reserved DP $F6/$F7 as a frame pointer.
|
||||
/// Set when the static frame size exceeds the 8-bit `,S` stack-rel
|
||||
/// addressing range (256 bytes); the prologue stores `S` (after
|
||||
/// local allocation) into $F6/$F7 (16-bit, bank-0 implicit), and
|
||||
/// eliminateFrameIndex routes any FI access whose effective offset
|
||||
/// exceeds 0xFF through `(F6),Y` indirect-indexed addressing.
|
||||
bool UsesDpFP = false;
|
||||
|
||||
|
||||
public:
|
||||
W65816MachineFunctionInfo() = default;
|
||||
|
|
@ -66,6 +74,9 @@ public:
|
|||
|
||||
bool getUsesAcc8() const { return UsesAcc8; }
|
||||
void setUsesAcc8(bool V) { UsesAcc8 = V; }
|
||||
|
||||
bool getUsesDpFP() const { return UsesDpFP; }
|
||||
void setUsesDpFP(bool V) { UsesDpFP = V; }
|
||||
};
|
||||
|
||||
} // namespace llvm
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
#include "W65816.h"
|
||||
#include "W65816FrameLowering.h"
|
||||
#include "W65816InstrInfo.h"
|
||||
#include "W65816MachineFunctionInfo.h"
|
||||
#include "W65816Subtarget.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
|
|
@ -25,6 +26,190 @@
|
|||
|
||||
using namespace llvm;
|
||||
|
||||
// IMG slot DP addresses for STAfi's IMG-source path.
|
||||
static int imgRegToDP(Register R) {
|
||||
switch (R) {
|
||||
case W65816::IMG0: return 0xD0;
|
||||
case W65816::IMG1: return 0xD2;
|
||||
case W65816::IMG2: return 0xD4;
|
||||
case W65816::IMG3: return 0xD6;
|
||||
case W65816::IMG4: return 0xD8;
|
||||
case W65816::IMG5: return 0xDA;
|
||||
case W65816::IMG6: return 0xDC;
|
||||
case W65816::IMG7: return 0xDE;
|
||||
case W65816::IMG8: return 0xC0;
|
||||
case W65816::IMG9: return 0xC2;
|
||||
case W65816::IMG10: return 0xC4;
|
||||
case W65816::IMG11: return 0xC6;
|
||||
case W65816::IMG12: return 0xC8;
|
||||
case W65816::IMG13: return 0xCA;
|
||||
case W65816::IMG14: return 0xCC;
|
||||
case W65816::IMG15: return 0xCE;
|
||||
default: return -1;
|
||||
}
|
||||
}
|
||||
|
||||
// Far FI elim via DP frame-pointer ($F6/$F7). Called when an FI's
|
||||
// effective offset exceeds 0xFF and the function reserved an FP at
|
||||
// prologue time (StackSize > 200). Stack is always bank 0, so
|
||||
// `(F6),Y` (16-bit DP-indirect, Y-indexed, bank-0 result) is correct.
|
||||
//
|
||||
// Common skeleton (varies per opcode):
|
||||
// PHY; LDY #FPOff; <op via ($F6),Y>; PLY
|
||||
// PHY/PLY balance, so subsequent `,S` accesses stay accurate. PLY
|
||||
// preserves C (only N/Z), so multi-precision carry chains survive
|
||||
// the load-via-Y.
|
||||
static bool expandFarFI(MachineInstr &MI, int FPOff,
|
||||
const W65816InstrInfo &TII) {
|
||||
MachineBasicBlock &MBB = *MI.getParent();
|
||||
MachineBasicBlock::iterator II = MI.getIterator();
|
||||
DebugLoc DL = MI.getDebugLoc();
|
||||
unsigned Opc = MI.getOpcode();
|
||||
|
||||
switch (Opc) {
|
||||
case W65816::LDAfi: {
|
||||
Register Dst = MI.getOperand(0).getReg();
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::PHY))
|
||||
.addReg(W65816::Y, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::LDY_Imm16))
|
||||
.addImm(FPOff)
|
||||
.addReg(W65816::Y, RegState::ImplicitDefine);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::LDA_DPIndY))
|
||||
.addImm(0xF6)
|
||||
.addReg(W65816::A, RegState::ImplicitDefine)
|
||||
.addReg(W65816::Y, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::PLY))
|
||||
.addReg(W65816::Y, RegState::ImplicitDefine);
|
||||
if (Dst == W65816::X)
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::TAX));
|
||||
else if (Dst == W65816::Y)
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::TAY));
|
||||
return true;
|
||||
}
|
||||
case W65816::STAfi: {
|
||||
Register Src = MI.getOperand(0).getReg();
|
||||
int srcDP = imgRegToDP(Src);
|
||||
if (srcDP >= 0)
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::LDA_DP)).addImm(srcDP);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::PHY))
|
||||
.addReg(W65816::Y, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::LDY_Imm16)).addImm(FPOff);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::STA_DPIndY))
|
||||
.addImm(0xF6)
|
||||
.addReg(W65816::A, RegState::Implicit)
|
||||
.addReg(W65816::Y, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::PLY));
|
||||
return true;
|
||||
}
|
||||
case W65816::STA8fi: {
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::SEP)).addImm(0x20)
|
||||
.addReg(W65816::P, RegState::ImplicitDefine);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::PHY))
|
||||
.addReg(W65816::Y, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::LDY_Imm16)).addImm(FPOff);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::STA_DPIndY))
|
||||
.addImm(0xF6)
|
||||
.addReg(W65816::A, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::PLY));
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::REP)).addImm(0x20)
|
||||
.addReg(W65816::P, RegState::ImplicitDefine);
|
||||
return true;
|
||||
}
|
||||
case W65816::ADCfi:
|
||||
case W65816::ADCEfi:
|
||||
case W65816::ANDfi:
|
||||
case W65816::ORAfi:
|
||||
case W65816::EORfi: {
|
||||
// Commutative (or chained): A op M. Save A to $E2, load M to A
|
||||
// via (F6),Y, then op against saved A. Order matters: PLY must
|
||||
// come BEFORE the final op so PLY's N/Z clobber doesn't hide the
|
||||
// op's flags from a downstream consumer.
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::STA_DP)).addImm(0xE2)
|
||||
.addReg(W65816::A, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::PHY))
|
||||
.addReg(W65816::Y, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::LDY_Imm16)).addImm(FPOff);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::LDA_DPIndY)).addImm(0xF6)
|
||||
.addReg(W65816::A, RegState::ImplicitDefine)
|
||||
.addReg(W65816::Y, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::PLY))
|
||||
.addReg(W65816::Y, RegState::ImplicitDefine);
|
||||
unsigned OpDPOpc = 0;
|
||||
switch (Opc) {
|
||||
case W65816::ADCfi:
|
||||
case W65816::ADCEfi: OpDPOpc = W65816::ADC_DP; break;
|
||||
case W65816::ANDfi: OpDPOpc = W65816::AND_DP; break;
|
||||
case W65816::ORAfi: OpDPOpc = W65816::ORA_DP; break;
|
||||
case W65816::EORfi: OpDPOpc = W65816::EOR_DP; break;
|
||||
default: llvm_unreachable("unhandled commutative far-FI");
|
||||
}
|
||||
auto B = BuildMI(MBB, II, DL, TII.get(OpDPOpc)).addImm(0xE2)
|
||||
.addReg(W65816::A, RegState::Implicit)
|
||||
.addReg(W65816::A, RegState::ImplicitDefine);
|
||||
if (OpDPOpc == W65816::ADC_DP) {
|
||||
B.addReg(W65816::P, RegState::Implicit)
|
||||
.addReg(W65816::P, RegState::ImplicitDefine);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
case W65816::SBCfi:
|
||||
case W65816::SBCEfi:
|
||||
case W65816::CMPfi: {
|
||||
// Non-commutative (A - M): we must load M into a scratch slot
|
||||
// without losing A. Sequence:
|
||||
// STA $E0 ; save original A
|
||||
// PHY
|
||||
// LDY #FPOff
|
||||
// LDA ($F6),Y ; A = M (lost saved A, but $E0 still has it)
|
||||
// STA $E2 ; $E2 = M
|
||||
// LDA $E0 ; A = original
|
||||
// PLY ; preserves C, clobbers N/Z (re-set by SBC/CMP)
|
||||
// SBC/CMP $E2
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::STA_DP)).addImm(0xE0)
|
||||
.addReg(W65816::A, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::PHY))
|
||||
.addReg(W65816::Y, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::LDY_Imm16)).addImm(FPOff);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::LDA_DPIndY)).addImm(0xF6)
|
||||
.addReg(W65816::A, RegState::ImplicitDefine)
|
||||
.addReg(W65816::Y, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::STA_DP)).addImm(0xE2)
|
||||
.addReg(W65816::A, RegState::Implicit);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::LDA_DP)).addImm(0xE0)
|
||||
.addReg(W65816::A, RegState::ImplicitDefine);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::PLY))
|
||||
.addReg(W65816::Y, RegState::ImplicitDefine);
|
||||
if (Opc == W65816::CMPfi) {
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::CMP_DP)).addImm(0xE2)
|
||||
.addReg(W65816::A, RegState::Implicit)
|
||||
.addReg(W65816::P, RegState::ImplicitDefine);
|
||||
} else {
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::SBC_DP)).addImm(0xE2)
|
||||
.addReg(W65816::A, RegState::Implicit)
|
||||
.addReg(W65816::A, RegState::ImplicitDefine)
|
||||
.addReg(W65816::P, RegState::Implicit)
|
||||
.addReg(W65816::P, RegState::ImplicitDefine);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
case W65816::ADDframe: {
|
||||
// LEA into A: A = FP + FPOff. 16-bit add, no carry chain needed.
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::LDA_DP)).addImm(0xF6)
|
||||
.addReg(W65816::A, RegState::ImplicitDefine);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::CLC))
|
||||
.addReg(W65816::P, RegState::ImplicitDefine);
|
||||
BuildMI(MBB, II, DL, TII.get(W65816::ADC_Imm16)).addImm(FPOff)
|
||||
.addReg(W65816::A, RegState::Implicit)
|
||||
.addReg(W65816::A, RegState::ImplicitDefine)
|
||||
.addReg(W65816::P, RegState::Implicit)
|
||||
.addReg(W65816::P, RegState::ImplicitDefine);
|
||||
return true;
|
||||
}
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
#define DEBUG_TYPE "w65816-reg-info"
|
||||
|
||||
#define GET_REGINFO_TARGET_DESC
|
||||
|
|
@ -83,8 +268,20 @@ bool W65816RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
int ImmOffset = MI.getOperand(FIOperandNum + 1).getImm();
|
||||
int Offset = FrameOffset + ImmOffset + (int)MFI.getStackSize() + SPAdj;
|
||||
if (FrameOffset < 0) Offset += 1;
|
||||
if (Offset < 0 || Offset > 0xFF)
|
||||
if (Offset < 0 || Offset > 0xFF) {
|
||||
// Far slot. Use FP if reserved. FP-relative offset excludes
|
||||
// SPAdj because $F6 captures S after prologue, before any
|
||||
// intermediate PUSH16 inside a call sequence.
|
||||
if (MF.getInfo<W65816MachineFunctionInfo>()->getUsesDpFP()) {
|
||||
int FPOff = FrameOffset + ImmOffset + (int)MFI.getStackSize();
|
||||
if (FrameOffset < 0) FPOff += 1;
|
||||
if (expandFarFI(MI, FPOff, TII)) {
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
report_fatal_error("W65816: frame offset out of stack-relative range");
|
||||
}
|
||||
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
|
||||
TII.get(W65816::LDA_StackRel))
|
||||
.addImm(Offset)
|
||||
|
|
@ -112,8 +309,17 @@ bool W65816RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
// in callee), so they don't need the skew.
|
||||
int Offset = FrameOffset + ImmOffset + (int)MFI.getStackSize() + SPAdj;
|
||||
if (FrameOffset < 0) Offset += 1;
|
||||
if (Offset < 0 || Offset > 0xFF)
|
||||
if (Offset < 0 || Offset > 0xFF) {
|
||||
if (MF.getInfo<W65816MachineFunctionInfo>()->getUsesDpFP()) {
|
||||
int FPOff = FrameOffset + ImmOffset + (int)MFI.getStackSize();
|
||||
if (FrameOffset < 0) FPOff += 1;
|
||||
if (expandFarFI(MI, FPOff, TII)) {
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
report_fatal_error("W65816: frame offset out of stack-relative range");
|
||||
}
|
||||
Register Src = MI.getOperand(0).getReg();
|
||||
int srcDP = -1;
|
||||
switch (Src) {
|
||||
|
|
@ -138,13 +344,18 @@ bool W65816RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
if (srcDP >= 0) {
|
||||
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
|
||||
TII.get(W65816::LDA_DP)).addImm(srcDP);
|
||||
} else if (Src == W65816::X || Src == W65816::Y) {
|
||||
// STAfi with X/Y source: regalloc occasionally lands a Wide16
|
||||
// vreg in $x/$y after class coalescing across an Idx16 source
|
||||
// (typically the i32-first-arg hi-half formal arg). Bridge
|
||||
// through A with TXA/TYA. Caller is responsible for ordering:
|
||||
// an arg0_lo STAfi $a must precede this so A's spill is already
|
||||
// saved when we clobber A. Without this bridge, the emitted
|
||||
// STA d,S stores stale A — observed as silent miscompile of i32
|
||||
// ptr formal args (`writeOne(arr)` storing 99 to wrong addr).
|
||||
unsigned XferOp = (Src == W65816::X) ? W65816::TXA : W65816::TYA;
|
||||
BuildMI(*MI.getParent(), II, MI.getDebugLoc(), TII.get(XferOp));
|
||||
}
|
||||
// Note: STAfi with X or Y source is NOT supported here — adding a
|
||||
// TXA/TYA pre-bracket would clobber A which a downstream STAfi $a
|
||||
// may still need (the prologue stashes arg0_lo from A and arg0_ml
|
||||
// from X via two adjacent STAfi, and putting A's STA *before* X's
|
||||
// is the caller's responsibility). storeRegToStackSlot already
|
||||
// bridges X/Y → A for spills it generates.
|
||||
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
|
||||
TII.get(W65816::STA_StackRel))
|
||||
.addImm(Offset)
|
||||
|
|
@ -175,8 +386,17 @@ bool W65816RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
int ImmOffset = MI.getOperand(FIOperandNum + 1).getImm();
|
||||
int Offset = FrameOffset + ImmOffset + (int)MFI.getStackSize() + SPAdj;
|
||||
if (FrameOffset < 0) Offset += 1; // empty-descending SP skew (see STAfi)
|
||||
if (Offset < 0 || Offset > 0xFF)
|
||||
if (Offset < 0 || Offset > 0xFF) {
|
||||
if (MF.getInfo<W65816MachineFunctionInfo>()->getUsesDpFP()) {
|
||||
int FPOff = FrameOffset + ImmOffset + (int)MFI.getStackSize();
|
||||
if (FrameOffset < 0) FPOff += 1;
|
||||
if (expandFarFI(MI, FPOff, TII)) {
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
report_fatal_error("W65816: frame offset out of stack-relative range");
|
||||
}
|
||||
BuildMI(*MI.getParent(), II, MI.getDebugLoc(), TII.get(W65816::SEP))
|
||||
.addImm(0x20)
|
||||
.addReg(W65816::P, RegState::ImplicitDefine);
|
||||
|
|
@ -201,6 +421,9 @@ bool W65816RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
int ImmOffset = MI.getOperand(FIOperandNum + 1).getImm();
|
||||
int Disp = FrameOffset + ImmOffset + (int)MFI.getStackSize() + SPAdj;
|
||||
if (FrameOffset < 0) Disp += 1; // empty-descending SP skew (see STAfi)
|
||||
// ADDframe (LEA) routes through TSC + ADC. Always works for any
|
||||
// 16-bit Disp via TSC's full-width 16-bit transfer, so we don't
|
||||
// need a far-FI variant here even when usesDpFP is true.
|
||||
if (Disp < 0 || Disp > 0xFFFF)
|
||||
report_fatal_error("W65816: frame offset out of i16 LEA range");
|
||||
// TSC: A = SP (implicit def of A, use of SP).
|
||||
|
|
@ -246,6 +469,22 @@ bool W65816RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|||
if (FrameOffset < 0) Offset += 1;
|
||||
|
||||
if (Offset < 0 || Offset > 0xFF) {
|
||||
if (MF.getInfo<W65816MachineFunctionInfo>()->getUsesDpFP()) {
|
||||
int FPOff = FrameOffset + ImmOffset + (int)MFI.getStackSize();
|
||||
if (FrameOffset < 0) FPOff += 1;
|
||||
// Emit the carry prefix (CLC/SEC) BEFORE the far-FI sequence —
|
||||
// expandFarFI's PHY/PLY pair preserves C, so the prefix's value
|
||||
// survives intact to the final ADC/SBC/CMP at the bottom of
|
||||
// the expansion.
|
||||
if (NeedsCarryPrefix) {
|
||||
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
|
||||
TII.get(IsSub ? W65816::SEC : W65816::CLC));
|
||||
}
|
||||
if (expandFarFI(MI, FPOff, TII)) {
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
}
|
||||
report_fatal_error("W65816: frame offset out of stack-relative range");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -105,6 +105,25 @@ static bool readsCarryOrV(const MachineInstr &MI) {
|
|||
case W65816::SBC_Imm8:
|
||||
case W65816::SBC_DP:
|
||||
case W65816::SBC_Abs:
|
||||
// Chained-carry pseudos. These run BEFORE AsmPrinter expansion so
|
||||
// we must whitelist them explicitly — they're the hi-half of any
|
||||
// multi-precision add/sub and read the lo-half's carry-out. Without
|
||||
// these, the INA/DEA peephole below silently rewrites a lo-half
|
||||
// `ADCi16imm src, 2` to `INA; INA` (which DOES NOT set C), breaking
|
||||
// the i32 ADD carry chain. Caught as `arr[0] = arr[1]` writing to
|
||||
// wrong bank under ptr32 because the high half got a stale C.
|
||||
case W65816::ADCEi16imm:
|
||||
case W65816::SBCEi16imm:
|
||||
// The fi/abs/imm forms of ADC/SBC are also pre-AsmPrinter pseudos;
|
||||
// each expands to a real ADC_/SBC_ opcode that reads carry.
|
||||
case W65816::ADCi16imm: // lo-half (CLC + ADC_Imm16)
|
||||
case W65816::SBCi16imm: // lo-half (SEC + SBC_Imm16)
|
||||
case W65816::ADCfi: // chained-carry stack form
|
||||
case W65816::SBCfi:
|
||||
case W65816::ADCEfi:
|
||||
case W65816::SBCEfi:
|
||||
case W65816::ADCabs:
|
||||
case W65816::SBCabs:
|
||||
case W65816::ROL_A: // rotates fold C in
|
||||
case W65816::ROR_A:
|
||||
case W65816::ROL_DP:
|
||||
|
|
|
|||
|
|
@ -733,7 +733,8 @@ bool W65816StackSlotCleanup::runOnMachineFunction(MachineFunction &MF) {
|
|||
case W65816::PHK:
|
||||
case W65816::TCS: case W65816::TXS:
|
||||
case W65816::TCD:
|
||||
case W65816::JSLpseudo: case W65816::JSL_Long:
|
||||
case W65816::JSLpseudo: case W65816::JSLpseudo32:
|
||||
case W65816::JSL_Long:
|
||||
case W65816::JSR_Abs:
|
||||
case W65816::JMP_Abs:
|
||||
case W65816::BRA:
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue