test_ll_prepend
---
1 (prev 9 next -1)
2 (prev 9 next 9)
3 (prev 9 next 9)
---
1 (prev 9 next -1)
2 (prev 9 next 1)
3 (prev 9 next 9)
---
1 (prev 9 next -1)
2 (prev 9 next 1)
3 (prev 9 next 2)
test_ll_append
---
1 (prev 9 next -1)
2 (prev 9 next 9)
3 (prev 9 next 9)
---
1 (prev 9 next 2)
2 (prev 9 next -1)
3 (prev 9 next 9)
---
1 (prev 9 next 2)
2 (prev 9 next 3)
3 (prev 9 next -1)
test_ll_prepend_elem
---
0 (prev 9 next -1)
1 (prev 9 next 9)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 9 next -1)
1 (prev 9 next 0)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 9 next 1)
1 (prev 9 next -1)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 9 next 1)
1 (prev 9 next -1)
2 (prev 9 next 0)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 9 next 2)
1 (prev 9 next -1)
2 (prev 9 next 1)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 9 next 2)
1 (prev 9 next 3)
2 (prev 9 next 1)
3 (prev 9 next -1)
4 (prev 9 next 9)
test_ll_append_elem
---
0 (prev 9 next -1)
1 (prev 9 next 9)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 9 next 1)
1 (prev 9 next -1)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 9 next 1)
1 (prev 9 next -1)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 9 next 2)
1 (prev 9 next -1)
2 (prev 9 next 1)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 9 next -1)
1 (prev 9 next 0)
2 (prev 9 next 1)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 9 next -1)
1 (prev 9 next 0)
2 (prev 9 next 1)
3 (prev 9 next 2)
4 (prev 9 next 9)
test_dl_prepend
---
1 (prev 1 next -1)
2 (prev 9 next 9)
3 (prev 9 next 9)
---
1 (prev 2 next -1)
2 (prev 1 next 1)
3 (prev 9 next 9)
---
1 (prev 2 next -1)
2 (prev 3 next 1)
3 (prev 1 next 2)
test_dl_append
---
1 (prev 1 next -1)
2 (prev 9 next 9)
3 (prev 9 next 9)
---
1 (prev 2 next 2)
2 (prev 1 next -1)
3 (prev 9 next 9)
---
1 (prev 3 next 2)
2 (prev 1 next 3)
3 (prev 2 next -1)
test_dl_prepend_elem
---
0 (prev 0 next -1)
1 (prev 9 next 9)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next -1)
1 (prev 0 next 0)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 1)
1 (prev 0 next -1)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 2 next 1)
1 (prev 0 next -1)
2 (prev 1 next 0)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 2)
1 (prev 2 next -1)
2 (prev 0 next 1)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 3 next 2)
1 (prev 2 next 3)
2 (prev 0 next 1)
3 (prev 1 next -1)
4 (prev 9 next 9)
test_dl_append_elem
---
0 (prev 0 next -1)
1 (prev 9 next 9)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 1)
1 (prev 0 next -1)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 1)
1 (prev 0 next -1)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 2)
1 (prev 2 next -1)
2 (prev 0 next 1)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next -1)
1 (prev 2 next 0)
2 (prev 0 next 1)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next -1)
1 (prev 2 next 0)
2 (prev 3 next 1)
3 (prev 0 next 2)
4 (prev 9 next 9)
test_cdl_prepend
---
1 (prev 1 next 1)
2 (prev 9 next 9)
3 (prev 9 next 9)
---
1 (prev 2 next 2)
2 (prev 1 next 1)
3 (prev 9 next 9)
---
1 (prev 2 next 3)
2 (prev 3 next 1)
3 (prev 1 next 2)
test_cdl_append
---
1 (prev 1 next 1)
2 (prev 9 next 9)
3 (prev 9 next 9)
---
1 (prev 2 next 2)
2 (prev 1 next 1)
3 (prev 9 next 9)
---
1 (prev 3 next 2)
2 (prev 1 next 3)
3 (prev 2 next 1)
test_cdl_prepend_elem
---
0 (prev 0 next 0)
1 (prev 9 next 9)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 1)
1 (prev 0 next 0)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 1)
1 (prev 0 next 0)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 2 next 1)
1 (prev 0 next 2)
2 (prev 1 next 0)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 2)
1 (prev 2 next 0)
2 (prev 0 next 1)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 3 next 2)
1 (prev 2 next 3)
2 (prev 0 next 1)
3 (prev 1 next 0)
4 (prev 9 next 9)
test_cdl_append_elem
---
0 (prev 0 next 0)
1 (prev 9 next 9)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 1)
1 (prev 0 next 0)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 1)
1 (prev 0 next 0)
2 (prev 9 next 9)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 2)
1 (prev 2 next 0)
2 (prev 0 next 1)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 2)
1 (prev 2 next 0)
2 (prev 0 next 1)
3 (prev 9 next 9)
4 (prev 9 next 9)
---
0 (prev 1 next 3)
1 (prev 2 next 0)
2 (prev 3 next 1)
3 (prev 0 next 2)
4 (prev 9 next 9)