From d626c54e927fe84b07a24fadfe8cc5d06363b55c Mon Sep 17 00:00:00 2001 From: Scott Duensing Date: Sat, 17 Oct 2026 15:40:15 -0500 Subject: [PATCH] Minor optimizations. --- demos/rsrcProbe.apl | Bin 47285 -> 47285 bytes .../lib/Target/W65816/W65816ISelLowering.cpp | 8 +++ .../lib/Target/W65816/W65816RegisterInfo.td | 11 ++-- .../test/CodeGen/W65816/fp-cmp-const-int.ll | 2 + .../test/CodeGen/W65816/select-same-arms.ll | 47 ++++++++++++++++++ 5 files changed, 64 insertions(+), 4 deletions(-) create mode 100644 src/llvm/test/CodeGen/W65816/select-same-arms.ll diff --git a/demos/rsrcProbe.apl b/demos/rsrcProbe.apl index 608b345f29aece63c597d7937a15de1bbf8e8741..ebaf67d4ec9bdc4d30dfb023a7c39721f84ab679 100644 GIT binary patch delta 6284 zcmcIoeN>d!nZNJ6GYrEp3^>3r4uoMCgsG7aKM}u(=#h^XByN%>U5y`z(ZFfljVH0j zlVRu0XiGX9-8ZKiYwE=7WSLP`8k$PCHsL@{3^~ck)N%+COQv8DyPjrZNt###`#kr~ z$9}Z`?Q*>Q?(_RS&%MvR@BP9zK3Bc*xvHm9D4)@gf%3Cwn!{(Bd$Nv%eT4ih?CBe` zU#TK@r{Sk#YM|VH(hg4ceT3N8D0_wNdH=D=|7I{SzRCWKj&!Zc*_TGFCx-}$s5)lt z4=XnWry8^ul?>HZL9cvQ^^kB*8B|@g>lZTbWbl@?owBAzFYBqc#vmI+y=DmaL_kkV^|9*02E#N1H{7RPUT6GI$bE zBMVeh7bda=EelIVgWjmh8Y=LLks1p%vXSbXq`!{zvsl?IY9fWy=oCmOmuiQEeh9fm z$T1_d|9j$+aXdP3)>5rE*++F=;seI3_IZ8$ezOW^$vsV|$b29j%)mhPIV~Dlhv6A51{cho2t(9* zCa4BRetfC@y9xhz9(?Ah5KSv;;tZiPO9(zZ8x%{`5Tr)jptz;l2Fklu zRoi#W&pxB_kIx@UC$M7QAfEA= zdBi_%*Y>999V%g;Qf8=2!cFKIQ{0C4g+66-+J51R(x3JL{QhU-TGQh?dP+Raj)(j( z>{!t)DW4cE*7pf5bk32XXGo-tsd;jK_#feTapx$e^uo&ULiGJK>a`0u?~1#D;up??4||9!v1PBpb$zY(Or~EDmM9yuOLQr4?Kosu z5z5oq_syGBbrVO-8JELV<+bb=h4spE^HZBt4t5{522>Crwn7kG#Rar*2rgr`t_rAT z!d5poV3S+K0=Va(uV0Yv*#^0=`(A@w(5;f>{BENB$-F4zOSESiWNY``205?$s|KYa zXLpXu0f#gM1_L6ygT(-x>4j9Ibm#05o>Vd|Mb^@9aA+Frx{&IiYe;h2*Jx^#hb#+( za^+de118ABDL@`@1;Sp(DG^WRfo6#Y~ZRxxjcWrkfbcK?h%HSm#kY;ZaWAL zLv*(*cdb8k*@}pJ{A+%6Zos26!{09pNBU{AxCI^}kb#cEQ-r@1;G|H~TCqN1C#z`_ z^exGv7=KTQ?mHrFhHSRPZdWTFJ8JB-PoVX+_-{*)HruP$xyYeIvau6hNJjQC^5TKn zc+DNg;Cx?3^M~h^J4ZTLzc{T$%}w6u?vnn zEQA_vtvEi<2z;IpHG9TjOkaDSOsQAPV040jjiKB{}`Jx|7d)D zMb}km>Uu~uHSWJYSnD63tcOmv;(EIj8X_e9SH4WBc}9Kn5XNwVL!J@%GM7SfzJF{m z-#_~4NY5755x!BOBUlBOTed zg>4RN&_BwTzPoKMw(?-&VHrhtgtp`9zsl<)^+OVgY>bK9F-nX@#WpRj;UG18cXv^f zcW)Ow#~<&4gUY+3tJAxyi(0&Ux@ea7$*$;L&JWUp=t|Ia2C1$V-h=&n@m;n-`8V5d zgsR?-f+q#lZHIE(ep#?7fx<09TJOEWO@ixWGu3!cHG``I9#H~$q2avO?3l21dM%Ct z+j)Bz`MqEx@Y9A$1yh#9l;nicz?8YL- zgtD0_55^R8LfOZZwwR)dDv!aW%1rXaBy}R_6{ehtDJco%5>tK|Q<4(OZ5@?61oy1DkX5G}JGNW=5S*(n!`&XDLnu9<<0v=E+r%@rlWPUZU* zP9aq}wAiY=S+O2!!s3I>-WFy5w3xG2<-sM$3E=r2t6@ydQdF__>e5ZT)~jB&PAH7$ z23`J)P)m?n?JZgoxHku{g5n@`+7BvwmT!R3onL+u0$-@KD%)4oL2c(stMc}WhoiM+ zl~{YBa(C3$uLQey=gRj~DtP)YT77>~xTf-(a82*_)n*}9KfJ~sub*3M6@)USf8Eoj zzP0{v8=U@X&xEaSE!1k%%J-_x@b|#Z>LU1kw7L*H&sUeB{gOYgdu@U>cVq$@yg`#ZQ#RoK;Gb@@{jM6S{)kgWB3VlH`Yb(j<#exM zeUc!QDw#E{@cU3r3H+ut%MGOu*aGX_znZmSMVYGE^;qcx{;7?BbdnCwUEBH^TYU{U z`0qwU+m;&la`f|0{SWaDWH%3DC#Ccu7UmW-zvJe&}-aWzgy|pT;cjcBspY815i$`Q~|6ZC+z?=@ZTZ;o5&g+ zKo5BaVURq$5+FieECXm1^a}yb3g=1ywy2o(lxo!iu#(kN*w~-dHxX897))|_HEE;> z$Q13pqAy$`acPdYv zwI7?GM7U^4!Y-bge;chNs|_vLTD=b7YVPw$K9KiB^%tUxY|2L@rM4>cdAWc^eA~_< zg7!2VOzQ&H#ngi1#bD`+TeJX8#RpRXUN2^vv4oMql1ZG4jiskm08f|h%m+AH%Cv#f zR4Z6F%MPRg%$Bh@S8+M>d9a*`7dezvFzX118yvPRX5rxU-A}e0w>AcR8$dtzhO)IT$OMHCDwY|C1^<`Cm4?`6?uwBr!0~%L6D^95Sk^|am0tD^9YYh0|;BCVT2vh zG{SD_F9>_3+&X}E>01cuGq!ZGOr z!b{Sx5l%`UyAV%HpCR}pQ$4^r$&Sz^RUllD>JWOQM-YB4wIlRN&mvrwjw19+T?lXU zWZsqDLF;{Pg`{g}4NG?rMx`Xo_d3_Y0J#5daC4f&Z4MC*GaSC+aE}9NWW!c-Nam2r zA)P}eha3*M9BdpM97+&i|J~2cat=#5RB~9&p_;=64z(O44$T}M;_xVktsHi6*v(-t zhjtG88Mw#+ZXV=tm_rAL=Q;eKu>_~>M~&|`0vv0cLU^fB-2`y5@fvEU8$U+yaX81J Xi^ByDJsf_{p^t<5GNAHzeY^e>`H%Fc delta 6321 zcmcIoe{|DTmVe)To2F?9X$T=nLv2W!wmCp)Ezm;wQ7C9zzkxEWoQR-TOQS|7H z?7H8QcY<0^2JpKhsPt^$ZJegsrB0Utk2?(0?wqwMZgd6)YU##Sdnmg)b<{0*SUFAzHOEOU zgfk}$V8uokXThE@raPMBlT$oG0W{XHo;K4uL_ zBr%s62c+{rjuWCDw!k56hukT`WNzvIQ;qfk~BG;#ruSWk64QWNcfQbs~#dsKM)~A>G+gD0dcC+LBP^ z&~XA)HphW5F>5%ds~ZHL2L& z){M2&LjuO|2s6O!k0$vFFe}s?LohS7h8QF%#$gtWp=UD2;2YB3tjAeZj~bRQhv~`? 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The i32 splits below make these + // -- a 0/1 boolean widened to i32 has 0 in both high halves -- and the + // DAG combiner never sees them, as the legalizer lowers each new i16 + // SELECT_CC at once. Left alone, each is a CMP, a branch to the next + // instruction and a spilled PHI. + if (TVal == FVal) + return TVal; + // i32 / i64 SELECT_CC. An i8/i16 result selects straight on the CMP/SBC // chain's flags (or on the equivalent i16 compare). An i32 result needs // two per-half selects and a glue value has only one consumer, so it diff --git a/src/llvm/lib/Target/W65816/W65816RegisterInfo.td b/src/llvm/lib/Target/W65816/W65816RegisterInfo.td index 01525bc..b29f5ff 100644 --- a/src/llvm/lib/Target/W65816/W65816RegisterInfo.td +++ b/src/llvm/lib/Target/W65816/W65816RegisterInfo.td @@ -50,10 +50,13 @@ def P : W65816Reg<8, "p">, DwarfRegNum<[8]>; // registers with cheap LDA/STA dp inter-register moves. This // relieves pressure on the single Acc16 register (A) so greedy // regalloc can succeed on functions with multiple simultaneously- -// live i16 vregs. Caller-save: callees may freely overwrite them, -// so regalloc spills around any call that might touch them. Their -// HWEncoding is never emitted (asmprinter translates IMGn references -// into LDA/STA dp with the right address). +// live i16 vregs. IMG0..IMG7 are caller-save: a call clobbers them, +// so regalloc spills around any call. IMG8..IMG15 are callee-saved: +// W65816ImgCalleeSave saves and restores them in any function that +// writes them, and callers keep values in them across calls, so hand +// asm called from C must not overwrite them without doing the same. +// Their HWEncoding is never emitted (asmprinter translates IMGn +// references into LDA/STA dp with the right address). // // Layout: IMG0..IMG7 at $D0..$DE (legacy slot block); IMG8..IMG15 // at $C0..$CE. Avoid stepping on user DP allocations below $C0. diff --git a/src/llvm/test/CodeGen/W65816/fp-cmp-const-int.ll b/src/llvm/test/CodeGen/W65816/fp-cmp-const-int.ll index e226fb2..baa35c4 100644 --- a/src/llvm/test/CodeGen/W65816/fp-cmp-const-int.ll +++ b/src/llvm/test/CodeGen/W65816/fp-cmp-const-int.ll @@ -70,6 +70,7 @@ define i16 @f_fabs_olt(float %x) { ; CHECK-NOT: jsl ; CHECK: and #0x7fff ; CHECK: cmp #0x4020 +; CHECK-NEXT: lda #0x1 ; CHECK-NEXT: bcc ; CHECK: rtl %a = call float @llvm.fabs.f32(float %x) @@ -84,6 +85,7 @@ define i16 @f_ogt0(float %x) { ; CHECK: adc #0xffff ; CHECK: adc #0xffff ; CHECK: cmp #0x7f80 +; CHECK-NEXT: lda #0x1 ; CHECK-NEXT: bcc ; CHECK: rtl %c = fcmp ogt float %x, 0.0 diff --git a/src/llvm/test/CodeGen/W65816/select-same-arms.ll b/src/llvm/test/CodeGen/W65816/select-same-arms.ll new file mode 100644 index 0000000..4ffd1a4 --- /dev/null +++ b/src/llvm/test/CodeGen/W65816/select-same-arms.ll @@ -0,0 +1,47 @@ +; A select whose two arms are the same value is that value: no compare, no +; branch. A 0/1 boolean widened to i32 (a returned bool, a zext to i32) is +; split into a select per half, and the high half's arms are both 0. The +; legalizer lowers each new i16 SELECT_CC at once, so the DAG combiner's +; same-arms fold never saw it: each one left a second compare of the value, +; a branch to the next instruction and a PHI spilled to a slot. +; +; RUN: llc -mtriple=w65816 -O2 < %s | FileCheck %s + +target triple = "w65816" + +@keys = external global [60 x i8] + +; One compare of the loaded byte, one branch on it. +define zeroext i1 @keyDown(i16 zeroext %key) { +; CHECK-LABEL: keyDown: +; CHECK: lda keys, x +; CHECK: bne .LBB0_3 +; CHECK-NOT: b{{eq|ne}} +; CHECK: rtl +entry: + %cmp = icmp ugt i16 %key, 59 + br i1 %cmp, label %return, label %if.end + +if.end: + %idx = zext nneg i16 %key to i32 + %p = getelementptr inbounds i8, ptr @keys, i32 %idx + %v = load i8, ptr %p, align 1 + %t = icmp ne i8 %v, 0 + br label %return + +return: + %r = phi i1 [ %t, %if.end ], [ false, %entry ] + ret i1 %r +} + +; The high half is the constant, the low half the one select. +define i32 @isZero32(i16 %a) { +; CHECK-LABEL: isZero32: +; CHECK: beq .LBB1_2 +; CHECK-NOT: b{{eq|ne}} +; CHECK: ldx #0x0 +; CHECK: rtl + %c = icmp eq i16 %a, 0 + %r = zext i1 %c to i32 + ret i32 %r +}