//===-- W65816.td - Describe the W65816 Target Machine -----*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// This is the top level entry point for the W65816 target.
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Target-independent interfaces
//===----------------------------------------------------------------------===//

include "llvm/Target/Target.td"

//===----------------------------------------------------------------------===//
// Subtarget Features.
//===----------------------------------------------------------------------===//

// Assembler-side M/X processor-status mode tracking.  These features let
// the AsmParser pick between the `_Imm8` and `_Imm16` forms of width-
// sensitive instructions (LDA/CMP/ADC/SBC/AND/ORA/EOR/BIT for M;
// LDX/LDY/CPX/CPY for X) when the user toggles via the .a8/.a16 and
// .i8/.i16 directives (with .as/.al/.xs/.xl WDC aliases).  Default
// processor is M=16, X=16 (FeatureMLow + FeatureXLow), matching the
// codegen ABI and preserving today's behavior for any .s that doesn't
// opt in.  The InstrInfo TSFlags MLow/MHigh/XLow/XHigh already exist on
// the per-instruction defs; this just exposes them as features the
// matcher Predicates can gate on.
def FeatureMLow  : SubtargetFeature<"mlow",  "MLow",  "true",
                                    "Accumulator is 16-bit (M flag = 0)">;
def FeatureMHigh : SubtargetFeature<"mhigh", "MHigh", "true",
                                    "Accumulator is 8-bit  (M flag = 1)">;
def FeatureXLow  : SubtargetFeature<"xlow",  "XLow",  "true",
                                    "Index regs are 16-bit (X flag = 0)">;
def FeatureXHigh : SubtargetFeature<"xhigh", "XHigh", "true",
                                    "Index regs are 8-bit  (X flag = 1)">;

// Assembler-side Predicates wrapping the features above.  The Imm8/Imm16
// instruction defs use these to gate the AsmMatcher (ISel patterns are
// unused on these defs — codegen emits the right opcode via direct
// BuildMI()).  Multi-inherit Predicate so the `Predicates` field accepts
// them; the CondString is trivial since no ISel pattern consults it.
def HasMLow  : Predicate<"true">, AssemblerPredicate<(all_of FeatureMLow),  "mlow">;
def HasMHigh : Predicate<"true">, AssemblerPredicate<(all_of FeatureMHigh), "mhigh">;
def HasXLow  : Predicate<"true">, AssemblerPredicate<(all_of FeatureXLow),  "xlow">;
def HasXHigh : Predicate<"true">, AssemblerPredicate<(all_of FeatureXHigh), "xhigh">;

//===----------------------------------------------------------------------===//
// W65816 supported processors.
//===----------------------------------------------------------------------===//
class Proc<string Name, list<SubtargetFeature> Features>
 : Processor<Name, NoItineraries, Features>;

// Default: native mode with 16-bit M and X (matches the C ABI).  The
// assembler can flip these per-section via .a8/.a16/.i8/.i16.
def : Proc<"generic", [FeatureMLow, FeatureXLow]>;
def : Proc<"w65816",  [FeatureMLow, FeatureXLow]>;

//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//

include "W65816RegisterInfo.td"

//===----------------------------------------------------------------------===//
// Calling Convention Description
//===----------------------------------------------------------------------===//

include "W65816CallingConv.td"

//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//

include "W65816InstrInfo.td"

defm : RemapAllTargetPseudoPointerOperands<PtrRegs>;

def W65816InstrInfo : InstrInfo;

//===---------------------------------------------------------------------===//
// Assembly Printers
//===---------------------------------------------------------------------===//

def W65816AsmWriter : AsmWriter {
  string AsmWriterClassName = "InstPrinter";
}

//===---------------------------------------------------------------------===//
// Assembly Parsers
//===---------------------------------------------------------------------===//

def W65816AsmParser : AsmParser;

//===----------------------------------------------------------------------===//
// Target Declaration
//===----------------------------------------------------------------------===//

def W65816 : Target {
  let InstructionSet = W65816InstrInfo;
  let AssemblyParsers = [W65816AsmParser];
}
