; Pin: i64-first-arg routes arg0 halves through Img16 (DP $C0..$DE).
;
; Without the Img16 routing, regalloc emits `TXA; STA spillA;
; STA spillX` at function entry — the TXA clobbers $a (arg0_lo)
; before the A-spill saves it, so both spill slots end up holding
; arg0_ml.  Caused __adddf3(1.5, 2.5) → 1.5.  See
; feedback_i64_first_arg_x_class.md.
;
; Fix: route arg0_lo via STA $dp and arg0_ml via STX $dp.  Visible at
; function entry as a pair of `stx 0x[cd]?` and `sta 0x[cd]?` writes
; into the IMG region of direct page.
;
; Trigger: i64 first arg with enough cross-call live range that arg0
; halves must be saved.
;
; RUN: llc -mtriple=w65816 -O2 < %s | FileCheck %s

declare i64 @ext1(i64 %x, i64 %y)
declare i64 @ext2(i64 %a)

define i64 @i64_first_pressure(i64 %x) {
; CHECK-LABEL: i64_first_pressure:
; Entry stores arg0_ml (X) and arg0_lo (A) into IMG slots, NOT a
; TXA-bridge sequence.  $D0 / $D2 are concrete IMG slots (the IMG
; region is $C0..$DE).  Match a stx in that range, followed by an
; sta in the same range, before the first jsl.
; CHECK:       stx 0x{{[cd]}}
; CHECK:       sta 0x{{[cd]}}
; CHECK:       jsl ext2
; CHECK:       rtl
entry:
  %a = call i64 @ext2(i64 %x)
  %b = add i64 %a, %x
  %c = call i64 @ext1(i64 %b, i64 %x)
  ret i64 %c
}
